Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3101477	1			T1	2		T2	1		T3	1
all_values[1]	3101477	1			T1	2		T2	1		T3	1
all_values[2]	3101477	1			T1	2		T2	1		T3	1
all_values[3]	3101477	1			T1	2		T2	1		T3	1
all_values[4]	3101477	1			T1	2		T2	1		T3	1
all_values[5]	3101477	1			T1	2		T2	1		T3	1
all_values[6]	3101477	1			T1	2		T2	1		T3	1
all_values[7]	3101477	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24540402

1

T1

16

T2

8

T3

8

auto[1]

271414

1

T24

56

T30

45

T31

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24785883

1

T1

16

T2

8

T3

8

auto[1]

25933

1

T11

47

T28

409

T55

267

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3080152	1			T1	2		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13166	1			T11	21		T28	200		T55	112
all_values[0]	auto[1]	auto[0]	7828	1			T24	3		T30	2		T32	12
all_values[0]	auto[1]	auto[1]	331	1			T24	2		T30	1		T31	1
all_values[1]	auto[0]	auto[0]	3043067	1			T1	2		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7588	1			T11	21		T28	149		T55	86
all_values[1]	auto[1]	auto[0]	50334	1			T24	2		T30	3		T31	1
all_values[1]	auto[1]	auto[1]	488	1			T24	5		T30	3		T31	1
all_values[2]	auto[0]	auto[0]	3091910	1			T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2595	1			T11	5		T28	60		T55	69
all_values[2]	auto[1]	auto[0]	6812	1			T24	5		T30	5		T183	1
all_values[2]	auto[1]	auto[1]	160	1			T24	4		T30	2		T31	1
all_values[3]	auto[0]	auto[0]	3090131	1			T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	154	1			T30	1		T31	1		T161	5
all_values[3]	auto[1]	auto[0]	11027	1			T24	5		T30	3		T31	1
all_values[3]	auto[1]	auto[1]	165	1			T24	3		T30	5		T32	3
all_values[4]	auto[0]	auto[0]	3059085	1			T1	2		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	153	1			T24	4		T30	3		T32	4
all_values[4]	auto[1]	auto[0]	42060	1			T24	2		T30	2		T31	4
all_values[4]	auto[1]	auto[1]	179	1			T24	1		T30	2		T31	1
all_values[5]	auto[0]	auto[0]	3062184	1			T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	161	1			T24	5		T30	2		T183	1
all_values[5]	auto[1]	auto[0]	38992	1			T24	4		T30	4		T31	3
all_values[5]	auto[1]	auto[1]	140	1			T24	3		T30	2		T31	2
all_values[6]	auto[0]	auto[0]	3029006	1			T1	2		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	181	1			T24	2		T30	1		T31	1
all_values[6]	auto[1]	auto[0]	72112	1			T24	4		T30	3		T31	1
all_values[6]	auto[1]	auto[1]	178	1			T24	4		T30	4		T31	3
all_values[7]	auto[0]	auto[0]	3060726	1			T1	2		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	143	1			T24	3		T30	2		T31	1
all_values[7]	auto[1]	auto[0]	40457	1			T24	3		T30	2		T31	4
all_values[7]	auto[1]	auto[1]	151	1			T24	6		T30	2		T32	10