Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32806	1			T3	12		T4	38		T11	44
auto[SpiFlashAddrCfg]	7864	1			T4	15		T11	19		T12	2
auto[SpiFlashAddr3b]	9232	1			T4	14		T11	11		T16	2
auto[SpiFlashAddr4b]	7716	1			T4	13		T11	17		T12	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32978

1

T3

12

T4

48

T11

52

auto[1]

24640

1

T4

32

T11

39

T18

26

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31418

1

T3

12

T4

39

T11

55

auto[1]

26200

1

T4

41

T11

36

T12

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37465	1			T3	12		T4	45		T11	56
values[1]	1090	1			T4	3		T11	1		T17	2
values[2]	1584	1			T4	1		T11	4		T14	1
values[3]	1468	1			T4	3		T11	2		T19	2
values[4]	1408	1			T17	6		T28	5		T39	7
values[5]	1485	1			T4	2		T11	1		T18	2
values[6]	1551	1			T4	3		T11	9		T38	1
values[7]	1436	1			T17	4		T38	3		T28	9
values[8]	10131	1			T4	23		T11	18		T12	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32525

1

T3

12

T12

12

T15

13

auto[1]

25093

1

T4

80

T11

91

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54278

1

T3

12

T4

66

T11

81

write

3340

1

T4

14

T11

10

T38

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19585

1

T3

12

T4

35

T11

34

valids[0x1]

38033

1

T4

45

T11

57

T12

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1570	1			T4	4		T11	1		T12	2
internal_process_ops[0x5a]	1631	1			T4	4		T11	1		T17	4
internal_process_ops[0x05]	18714	1			T4	2		T11	12		T15	7
internal_process_ops[0x35]	1591	1			T4	3		T11	2		T12	2
internal_process_ops[0x15]	1557	1			T4	2		T11	3		T28	10
internal_process_ops[0x03]	1078	1			T4	1		T11	1		T17	2
internal_process_ops[0x0b]	1154	1			T4	2		T16	2		T17	2
internal_process_ops[0x3b]	1123	1			T4	2		T12	4		T16	2
internal_process_ops[0x6b]	1100	1			T4	1		T11	1		T15	2
internal_process_ops[0xbb]	1072	1			T11	1		T12	2		T19	2
internal_process_ops[0xeb]	1124	1			T4	1		T14	1		T28	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55906

1

T3

12

T4

71

T11

86

auto[1]

1712

1

T4

9

T11

5

T38

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55244

1

T3

12

T4

70

T11

86

auto[1]

2374

1

T4

10

T11

5

T15

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10111

1

T3

12

T12

4

T15

9

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6865

1

T18

8

T28

32

T39

167

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2373

1

T12

2

T15

4

T19

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1945

1

T28

33

T39

18

T50

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2757

1

T17

4

T28

18

T39

25

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2420

1

T18

6

T28

32

T39

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2221

1

T12

6

T17

12

T19

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2059

1

T18

12

T28

29

T39

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

107

1

T39

2

T40

6

T22

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

122

1

T28

1

T39

4

T40

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T39

1

T23

1

T49

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

115

1

T46

1

T47

1

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T28

4

T23

1

T185

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T28

1

T40

2

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

109

1

T28

1

T39

2

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

115

1

T40

1

T47

1

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

126

1

T28

2

T40

1

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T28

2

T46

1

T47

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T28

1

T39

1

T47

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T39

1

T40

5

T85

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

132

1

T28

2

T22

1

T186

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

99

1

T39

1

T50

1

T40

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T28

2

T39

4

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

137

1

T28

3

T40

2

T22

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9382

1

T4

24

T11

27

T38

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5585

1

T4

8

T11

12

T38

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1386

1

T4

6

T11

5

T16

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1297

1

T4

8

T11

11

T38

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1666

1

T4

3

T11

7

T16

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1601

1

T4

6

T11

2

T38

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1373

1

T4

10

T11

6

T14

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1237

1

T4

1

T11

11

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T4

2

T11

3

T55

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

104

1

T82

2

T31

2

T99

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T4

1

T71

1

T187

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

109

1

T4

3

T11

2

T38

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T11

2

T55

3

T187

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

114

1

T58

1

T187

5

T188

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T4

1

T82

7

T99

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T11

1

T72

2

T187

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

77

1

T55

1

T189

1

T190

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T4

3

T11

2

T187

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T71

1

T31

5

T100

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T4

2

T55

2

T58

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T55

2

T187

1

T82

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

87

1

T58

1

T187

2

T30

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

81

1

T4

1

T55

2

T187

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T4

1

T55

1

T187

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4333	1			T3	12		T15	2		T28	56
auto[0]	values[0]	valids[0x1]	15865	1			T12	4		T15	9		T17	2
auto[0]	values[1]	valids[0x1]	619	1			T17	2		T18	2		T28	5
auto[0]	values[2]	valids[0x0]	636	1			T17	4		T18	6		T28	3
auto[0]	values[2]	valids[0x1]	313	1			T28	7		T39	3		T101	2
auto[0]	values[3]	valids[0x0]	542	1			T19	2		T28	7		T39	6
auto[0]	values[3]	valids[0x1]	312	1			T28	8		T39	1		T46	1
auto[0]	values[4]	valids[0x0]	569	1			T28	4		T39	5		T46	1
auto[0]	values[4]	valids[0x1]	344	1			T17	6		T28	1		T39	2
auto[0]	values[5]	valids[0x0]	639	1			T18	2		T28	5		T39	5
auto[0]	values[5]	valids[0x1]	346	1			T28	4		T39	4		T46	4
auto[0]	values[6]	valids[0x0]	601	1			T28	3		T39	4		T40	11
auto[0]	values[6]	valids[0x1]	335	1			T28	6		T39	1		T46	2
auto[0]	values[7]	valids[0x0]	587	1			T17	4		T28	4		T39	5
auto[0]	values[7]	valids[0x1]	313	1			T28	5		T39	5		T50	1
auto[0]	values[8]	valids[0x0]	3861	1			T12	8		T15	2		T19	2
auto[0]	values[8]	valids[0x1]	2310	1			T18	10		T28	39		T39	26
auto[1]	values[0]	valids[0x0]	3570	1			T4	20		T11	15		T38	5
auto[1]	values[0]	valids[0x1]	13697	1			T4	25		T11	41		T16	2
auto[1]	values[1]	valids[0x1]	471	1			T4	3		T11	1		T55	1
auto[1]	values[2]	valids[0x0]	383	1			T4	1		T14	1		T16	2
auto[1]	values[2]	valids[0x1]	252	1			T11	4		T55	1		T71	1
auto[1]	values[3]	valids[0x0]	356	1			T11	2		T55	4		T72	5
auto[1]	values[3]	valids[0x1]	258	1			T4	3		T55	5		T72	2
auto[1]	values[4]	valids[0x0]	279	1			T55	1		T58	4		T71	1
auto[1]	values[4]	valids[0x1]	216	1			T55	1		T72	1		T187	4
auto[1]	values[5]	valids[0x0]	282	1			T4	2		T38	1		T55	4
auto[1]	values[5]	valids[0x1]	218	1			T11	1		T38	2		T55	1
auto[1]	values[6]	valids[0x0]	365	1			T11	4		T38	1		T55	3
auto[1]	values[6]	valids[0x1]	250	1			T4	3		T11	5		T55	4
auto[1]	values[7]	valids[0x0]	309	1			T38	2		T55	1		T187	2
auto[1]	values[7]	valids[0x1]	227	1			T38	1		T55	4		T58	3
auto[1]	values[8]	valids[0x0]	2273	1			T4	12		T11	13		T38	4
auto[1]	values[8]	valids[0x1]	1687	1			T4	11		T11	5		T38	1