Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3368888

1

T3

19

T4

4525

T11

1694

auto[1]

30121

1

T4

67

T11

11

T15

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

891538

1

T3

19

T4

201

T11

30

auto[1]

2507471

1

T4

4391

T11

1675

T15

7

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	603397	1			T4	1237		T11	277		T12	1
auto[524288:1048575]	445204	1			T4	15		T11	1		T38	6
auto[1048576:1572863]	421742	1			T3	10		T14	247		T16	3881
auto[1572864:2097151]	417526	1			T4	286		T14	81		T28	1300
auto[2097152:2621439]	342125	1			T3	5		T4	32		T11	513
auto[2621440:3145727]	398433	1			T3	4		T11	10		T14	6
auto[3145728:3670015]	389332	1			T4	3006		T11	132		T14	2
auto[3670016:4194303]	381250	1			T4	16		T11	772		T14	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2541776

1

T3

13

T4

4584

T11

1704

auto[1]

857233

1

T3

6

T4

8

T11

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2950331

1

T3

9

T4

4558

T11

1448

auto[1]

448678

1

T3

10

T4

34

T11

257

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	166825	1			T4	45		T11	8		T12	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	386052	1			T4	1136		T11	3		T15	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	109590	1			T4	15		T11	1		T38	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	260362	1			T28	116		T39	515		T55	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	113920	1			T14	247		T16	3881		T38	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232580	1			T28	514		T39	2585		T55	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97475	1			T4	23		T14	81		T28	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	261738	1			T4	256		T28	1287		T39	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94502	1			T3	5		T4	20		T11	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	189852	1			T4	5		T11	512		T28	3884
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	86041	1			T3	4		T11	6		T14	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	260706	1			T11	2		T28	2579		T39	3429
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	127213	1			T4	18		T11	4		T14	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207556	1			T4	2973		T11	128		T28	2891
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	84516	1			T4	6		T11	4		T14	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	246300	1			T11	768		T28	256		T39	257
auto[0]	auto[1]	auto[0:524287]	auto[0]	1060	1			T4	21		T11	1		T50	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	43967	1			T11	256		T28	299		T72	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	527	1			T46	1		T40	3		T22	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71095	1			T46	616		T22	1		T187	2190
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	585	1			T3	10		T38	14		T39	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	69791	1			T38	512		T55	1833		T47	1809
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	799	1			T39	3		T50	2		T71	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	53037	1			T47	1		T187	3		T23	2320
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1277	1			T55	2		T58	6		T47	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53397	1			T55	768		T47	1		T22	134
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	619	1			T28	3		T39	2		T55	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47902	1			T28	5137		T55	4666		T58	212
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1966	1			T28	1		T39	2		T55	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49656	1			T28	256		T39	1		T55	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	671	1			T4	7		T38	11		T28	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	47311	1			T28	256		T39	256		T55	900
auto[1]	auto[0]	auto[0:524287]	auto[0]	497	1			T4	16		T11	3		T15	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4014	1			T4	16		T11	6		T15	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	388	1			T28	2		T39	3		T50	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2481	1			T28	3		T39	37		T55	18
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	452	1			T28	2		T39	3		T55	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3916	1			T28	2		T39	69		T55	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	431	1			T4	7		T28	2		T71	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3176	1			T28	1		T71	24		T40	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	369	1			T4	7		T39	1		T55	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2249	1			T39	2		T55	7		T82	16
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	395	1			T11	2		T28	1		T39	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2360	1			T39	20		T55	4		T71	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	348	1			T4	10		T28	4		T39	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2072	1			T4	5		T28	1		T39	53
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	356	1			T39	1		T71	1		T40	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1599	1			T39	14		T23	26		T82	49
auto[1]	auto[1]	auto[0:524287]	auto[0]	106	1			T4	3		T187	1		T30	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	876	1			T34	26		T205	21		T241	19
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	77	1			T22	1		T49	1		T34	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	684	1			T22	2		T49	1		T34	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	84	1			T55	1		T47	1		T189	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	414	1			T55	1		T47	5		T205	56
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	111	1			T47	1		T187	3		T85	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	759	1			T47	4		T187	54		T85	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	80	1			T47	1		T22	1		T42	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	399	1			T47	19		T42	5		T82	32
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	91	1			T58	3		T40	1		T82	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	319	1			T58	63		T82	8		T185	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	93	1			T39	1		T55	1		T40	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	428	1			T39	7		T55	15		T40	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	74	1			T4	3		T38	3		T55	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	423	1			T55	26		T23	3		T82	24

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2071457	1			T3	9		T4	4497		T11	1437
auto[0]	auto[0]	auto[1]	853771	1			T14	502		T16	8523		T39	6
auto[0]	auto[1]	auto[0]	440908	1			T3	4		T4	28		T11	257
auto[0]	auto[1]	auto[1]	2752	1			T3	6		T55	1		T187	1
auto[1]	auto[0]	auto[0]	24529	1			T4	54		T11	10		T15	6
auto[1]	auto[0]	auto[1]	574	1			T4	7		T11	1		T15	1
auto[1]	auto[1]	auto[0]	4882	1			T4	5		T38	2		T39	8
auto[1]	auto[1]	auto[1]	136	1			T4	1		T38	1		T58	1