Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3101477	1			T1	2		T2	1		T3	1
all_pins[1]	3101477	1			T1	2		T2	1		T3	1
all_pins[2]	3101477	1			T1	2		T2	1		T3	1
all_pins[3]	3101477	1			T1	2		T2	1		T3	1
all_pins[4]	3101477	1			T1	2		T2	1		T3	1
all_pins[5]	3101477	1			T1	2		T2	1		T3	1
all_pins[6]	3101477	1			T1	2		T2	1		T3	1
all_pins[7]	3101477	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24736872	1			T1	16		T2	8		T3	8
values[0x1]	74944	1			T24	28		T30	21		T31	9
transitions[0x0=>0x1]	73459	1			T24	18		T30	17		T31	6
transitions[0x1=>0x0]	73470	1			T24	19		T30	17		T31	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3101127	1			T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	350	1			T24	2		T30	1		T31	1
all_pins[0]	transitions[0x0=>0x1]	188	1			T24	1		T30	1		T31	1
all_pins[0]	transitions[0x1=>0x0]	363	1			T24	4		T30	3		T31	1
all_pins[1]	values[0x0]	3100952	1			T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	525	1			T24	5		T30	3		T31	1
all_pins[1]	transitions[0x0=>0x1]	481	1			T24	3		T30	3		T183	2
all_pins[1]	transitions[0x1=>0x0]	118	1			T24	2		T30	2		T32	3
all_pins[2]	values[0x0]	3101315	1			T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	162	1			T24	4		T30	2		T31	1
all_pins[2]	transitions[0x0=>0x1]	115	1			T24	3		T30	1		T31	1
all_pins[2]	transitions[0x1=>0x0]	118	1			T24	2		T30	4		T32	2
all_pins[3]	values[0x0]	3101312	1			T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	165	1			T24	3		T30	5		T32	3
all_pins[3]	transitions[0x0=>0x1]	127	1			T24	3		T30	4		T33	2
all_pins[3]	transitions[0x1=>0x0]	141	1			T24	1		T30	1		T31	1
all_pins[4]	values[0x0]	3101298	1			T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	179	1			T24	1		T30	2		T31	1
all_pins[4]	transitions[0x0=>0x1]	141	1			T24	1		T30	2		T183	3
all_pins[4]	transitions[0x1=>0x0]	1442	1			T24	3		T30	2		T31	1
all_pins[5]	values[0x0]	3099997	1			T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	1480	1			T24	3		T30	2		T31	2
all_pins[5]	transitions[0x0=>0x1]	409	1			T24	2		T30	1		T31	1
all_pins[5]	transitions[0x1=>0x0]	70861	1			T24	3		T30	3		T31	2
all_pins[6]	values[0x0]	3029545	1			T1	2		T2	1		T3	1
all_pins[6]	values[0x1]	71932	1			T24	4		T30	4		T31	3
all_pins[6]	transitions[0x0=>0x1]	71889	1			T24	1		T30	3		T31	3
all_pins[6]	transitions[0x1=>0x0]	108	1			T24	3		T30	1		T32	7
all_pins[7]	values[0x0]	3101326	1			T1	2		T2	1		T3	1
all_pins[7]	values[0x1]	151	1			T24	6		T30	2		T32	10
all_pins[7]	transitions[0x0=>0x1]	109	1			T24	4		T30	2		T32	9
all_pins[7]	transitions[0x1=>0x0]	319	1			T24	1		T30	1		T31	1