Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18358

1

T3

12

T12

12

T15

13

auto[1]

14167

1

T18

26

T28

133

T39

230

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5145	1			T28	84		T46	21		T40	20
values[1]	3676	1			T3	12		T39	20		T40	24
values[2]	4249	1			T19	14		T28	48		T46	20
values[3]	3743	1			T28	40		T39	20		T47	40
values[4]	3912	1			T28	21		T39	232		T129	22
values[5]	4136	1			T17	18		T28	65		T39	35
values[6]	3436	1			T12	12		T15	13		T18	26
values[7]	4228	1			T39	142		T52	10		T40	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3480	1			T18	26		T28	20		T39	20
values[1]	4292	1			T19	14		T28	67		T39	75
values[2]	4228	1			T15	13		T28	22		T39	92
values[3]	4163	1			T28	20		T39	63		T101	8
values[4]	3566	1			T3	12		T17	18		T39	20
values[5]	4894	1			T28	22		T39	159		T40	40
values[6]	4295	1			T12	12		T28	126		T129	22
values[7]	3607	1			T28	21		T39	20		T46	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	207	1			T150	14		T185	16		T242	10
auto[0]	values[0]	values[1]	486	1			T28	13		T243	6		T244	20
auto[0]	values[0]	values[2]	386	1			T40	6		T245	2		T147	16
auto[0]	values[0]	values[3]	308	1			T28	15		T46	15		T234	10
auto[0]	values[0]	values[4]	223	1			T22	10		T185	10		T85	13
auto[0]	values[0]	values[5]	390	1			T185	9		T85	10		T205	12
auto[0]	values[0]	values[6]	364	1			T28	28		T22	34		T33	13
auto[0]	values[0]	values[7]	323	1			T205	76		T218	16		T184	7
auto[0]	values[1]	values[0]	333	1			T39	9		T40	18		T197	16
auto[0]	values[1]	values[1]	262	1			T85	27		T226	12		T237	8
auto[0]	values[1]	values[2]	281	1			T23	24		T42	14		T197	13
auto[0]	values[1]	values[3]	107	1			T246	11		T96	12		T247	15
auto[0]	values[1]	values[4]	225	1			T3	12		T219	8		T248	11
auto[0]	values[1]	values[5]	383	1			T210	2		T42	16		T249	18
auto[0]	values[1]	values[6]	329	1			T250	4		T202	10		T218	10
auto[0]	values[1]	values[7]	239	1			T42	30		T49	12		T226	13
auto[0]	values[2]	values[0]	181	1			T251	4		T83	11		T33	7
auto[0]	values[2]	values[1]	257	1			T19	14		T28	17		T46	13
auto[0]	values[2]	values[2]	198	1			T23	15		T185	12		T197	7
auto[0]	values[2]	values[3]	507	1			T208	2		T42	13		T197	7
auto[0]	values[2]	values[4]	273	1			T42	6		T94	10		T49	12
auto[0]	values[2]	values[5]	300	1			T185	11		T205	11		T217	17
auto[0]	values[2]	values[6]	393	1			T28	10		T23	40		T185	10
auto[0]	values[2]	values[7]	194	1			T200	9		T242	8		T222	15
auto[0]	values[3]	values[0]	205	1			T185	12		T202	16		T83	15
auto[0]	values[3]	values[1]	171	1			T47	31		T42	12		T197	5
auto[0]	values[3]	values[2]	218	1			T205	12		T217	9		T226	13
auto[0]	values[3]	values[3]	262	1			T42	13		T49	12		T185	15
auto[0]	values[3]	values[4]	306	1			T39	11		T89	8		T83	14
auto[0]	values[3]	values[5]	373	1			T186	22		T175	16		T202	21
auto[0]	values[3]	values[6]	266	1			T28	16		T185	59		T197	16
auto[0]	values[3]	values[7]	298	1			T85	13		T205	13		T202	12
auto[0]	values[4]	values[0]	283	1			T185	12		T197	16		T33	14
auto[0]	values[4]	values[1]	396	1			T39	13		T40	21		T47	11
auto[0]	values[4]	values[2]	253	1			T39	13		T217	13		T252	4
auto[0]	values[4]	values[3]	291	1			T39	10		T183	16		T200	16
auto[0]	values[4]	values[4]	245	1			T40	11		T22	8		T253	12
auto[0]	values[4]	values[5]	364	1			T39	12		T40	11		T181	18
auto[0]	values[4]	values[6]	215	1			T129	22		T254	2		T217	14
auto[0]	values[4]	values[7]	127	1			T28	14		T237	11		T255	9
auto[0]	values[5]	values[0]	263	1			T235	6		T217	13		T218	54
auto[0]	values[5]	values[1]	297	1			T28	11		T39	32		T47	7
auto[0]	values[5]	values[2]	440	1			T28	11		T46	91		T256	4
auto[0]	values[5]	values[3]	282	1			T22	14		T205	13		T257	18
auto[0]	values[5]	values[4]	235	1			T17	18		T50	8		T23	12
auto[0]	values[5]	values[5]	263	1			T28	7		T40	8		T41	8
auto[0]	values[5]	values[6]	455	1			T40	9		T47	11		T49	10
auto[0]	values[5]	values[7]	282	1			T47	21		T185	8		T83	8
auto[0]	values[6]	values[0]	292	1			T28	15		T258	2		T259	4
auto[0]	values[6]	values[1]	308	1			T47	50		T93	12		T260	6
auto[0]	values[6]	values[2]	248	1			T15	13		T22	9		T23	13
auto[0]	values[6]	values[3]	177	1			T101	8		T40	17		T205	11
auto[0]	values[6]	values[4]	179	1			T40	10		T185	10		T85	10
auto[0]	values[6]	values[5]	331	1			T22	10		T197	10		T205	12
auto[0]	values[6]	values[6]	245	1			T12	12		T28	8		T40	6
auto[0]	values[6]	values[7]	238	1			T46	6		T23	13		T217	17
auto[0]	values[7]	values[0]	237	1			T23	12		T197	12		T202	10
auto[0]	values[7]	values[1]	376	1			T39	14		T261	18		T262	14
auto[0]	values[7]	values[2]	245	1			T198	9		T263	14		T264	40
auto[0]	values[7]	values[3]	634	1			T40	16		T220	10		T42	10
auto[0]	values[7]	values[4]	210	1			T52	10		T49	12		T230	2
auto[0]	values[7]	values[5]	286	1			T39	95		T49	6		T185	5
auto[0]	values[7]	values[6]	184	1			T201	26		T265	8		T89	12
auto[0]	values[7]	values[7]	229	1			T39	10		T22	11		T23	9
auto[1]	values[0]	values[0]	258	1			T185	6		T242	10		T231	85
auto[1]	values[0]	values[1]	252	1			T28	8		T197	10		T205	11
auto[1]	values[0]	values[2]	379	1			T40	14		T218	15		T89	8
auto[1]	values[0]	values[3]	228	1			T28	5		T46	6		T266	10
auto[1]	values[0]	values[4]	193	1			T22	12		T185	20		T85	7
auto[1]	values[0]	values[5]	505	1			T185	146		T85	17		T205	8
auto[1]	values[0]	values[6]	361	1			T28	15		T22	10		T33	125
auto[1]	values[0]	values[7]	282	1			T48	14		T205	3		T218	4
auto[1]	values[1]	values[0]	121	1			T39	11		T40	6		T267	4
auto[1]	values[1]	values[1]	304	1			T85	13		T226	23		T237	12
auto[1]	values[1]	values[2]	318	1			T23	22		T42	24		T197	7
auto[1]	values[1]	values[3]	128	1			T229	14		T246	9		T96	8
auto[1]	values[1]	values[4]	216	1			T248	9		T200	37		T268	19
auto[1]	values[1]	values[5]	128	1			T42	4		T184	9		T269	8
auto[1]	values[1]	values[6]	126	1			T202	29		T218	10		T83	7
auto[1]	values[1]	values[7]	176	1			T42	12		T49	9		T226	7
auto[1]	values[2]	values[0]	172	1			T83	9		T33	13		T270	14
auto[1]	values[2]	values[1]	247	1			T28	8		T46	7		T40	6
auto[1]	values[2]	values[2]	159	1			T23	6		T185	8		T197	13
auto[1]	values[2]	values[3]	258	1			T42	7		T197	13		T89	12
auto[1]	values[2]	values[4]	181	1			T42	14		T49	8		T202	13
auto[1]	values[2]	values[5]	360	1			T185	39		T205	17		T217	3
auto[1]	values[2]	values[6]	348	1			T28	13		T23	7		T185	56
auto[1]	values[2]	values[7]	221	1			T200	44		T242	12		T222	5
auto[1]	values[3]	values[0]	137	1			T185	8		T202	6		T83	5
auto[1]	values[3]	values[1]	95	1			T47	9		T42	8		T197	15
auto[1]	values[3]	values[2]	213	1			T205	42		T217	11		T226	7
auto[1]	values[3]	values[3]	170	1			T42	7		T49	9		T185	5
auto[1]	values[3]	values[4]	297	1			T39	9		T89	12		T83	6
auto[1]	values[3]	values[5]	235	1			T202	8		T183	8		T83	11
auto[1]	values[3]	values[6]	205	1			T28	24		T185	13		T197	4
auto[1]	values[3]	values[7]	292	1			T85	7		T205	14		T202	8
auto[1]	values[4]	values[0]	190	1			T185	8		T197	4		T33	11
auto[1]	values[4]	values[1]	272	1			T39	7		T40	7		T47	69
auto[1]	values[4]	values[2]	247	1			T39	79		T217	7		T199	7
auto[1]	values[4]	values[3]	232	1			T39	53		T183	7		T200	4
auto[1]	values[4]	values[4]	228	1			T40	9		T22	12		T183	7
auto[1]	values[4]	values[5]	266	1			T39	45		T40	9		T271	4
auto[1]	values[4]	values[6]	206	1			T217	10		T222	25		T151	12
auto[1]	values[4]	values[7]	97	1			T28	7		T237	11		T255	11
auto[1]	values[5]	values[0]	87	1			T217	12		T218	3		T211	20
auto[1]	values[5]	values[1]	301	1			T28	10		T39	3		T47	13
auto[1]	values[5]	values[2]	216	1			T28	11		T46	12		T23	2
auto[1]	values[5]	values[3]	148	1			T22	6		T205	7		T83	10
auto[1]	values[5]	values[4]	152	1			T50	12		T23	8		T272	8
auto[1]	values[5]	values[5]	160	1			T28	15		T40	12		T85	11
auto[1]	values[5]	values[6]	354	1			T40	11		T47	21		T49	12
auto[1]	values[5]	values[7]	201	1			T47	7		T185	58		T83	12
auto[1]	values[6]	values[0]	189	1			T18	26		T28	5		T23	8
auto[1]	values[6]	values[1]	116	1			T47	4		T198	12		T268	7
auto[1]	values[6]	values[2]	248	1			T22	12		T23	30		T89	6
auto[1]	values[6]	values[3]	98	1			T40	6		T205	9		T273	5
auto[1]	values[6]	values[4]	152	1			T40	19		T185	10		T85	18
auto[1]	values[6]	values[5]	295	1			T22	10		T197	10		T205	61
auto[1]	values[6]	values[6]	142	1			T28	12		T40	16		T200	10
auto[1]	values[6]	values[7]	178	1			T46	14		T23	7		T233	12
auto[1]	values[7]	values[0]	325	1			T23	8		T197	8		T202	143
auto[1]	values[7]	values[1]	152	1			T39	6		T205	10		T226	5
auto[1]	values[7]	values[2]	179	1			T198	11		T263	6		T274	10
auto[1]	values[7]	values[3]	333	1			T40	4		T42	54		T218	8
auto[1]	values[7]	values[4]	251	1			T49	10		T89	7		T33	126
auto[1]	values[7]	values[5]	255	1			T39	7		T49	14		T185	15
auto[1]	values[7]	values[6]	102	1			T89	8		T33	9		T275	9
auto[1]	values[7]	values[7]	230	1			T39	10		T22	27		T23	83