Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	468	1			T28	5		T39	5		T46	4
auto[ReadAddrCrossIntoMailbox]	304	1			T28	5		T39	4		T46	3
auto[ReadAddrCrossOutOfMailbox]	341	1			T28	5		T39	6		T46	3
auto[ReadAddrCrossAllMailbox]	234	1			T28	1		T39	3		T40	6
auto[ReadAddrOutsideMailbox]	3950	1			T12	6		T15	2		T17	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2559

1

T12

3

T15

1

T17

2

auto[1]

2738

1

T12

3

T15

1

T17

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	821	1			T17	2		T18	2		T19	2
read_ops[0x0b]	934	1			T17	2		T18	2		T28	11
read_ops[0x3b]	901	1			T12	4		T28	13		T39	9
read_ops[0x6b]	885	1			T15	2		T19	2		T28	10
read_ops[0xbb]	856	1			T12	2		T19	2		T28	11
read_ops[0xeb]	900	1			T28	7		T39	9		T46	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T28	1		T258	1		T220	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T46	2		T258	1		T220	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T28	1		T202	2		T217	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T28	1		T39	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T85	1		T202	1		T276	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T46	1		T85	2		T200	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T40	1		T41	1		T83	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T28	1		T40	1		T47	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T17	1		T18	1		T19	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T17	1		T18	1		T19	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T39	1		T220	1		T42	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T220	1		T42	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T39	1		T22	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T28	1		T47	2		T202	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T28	1		T39	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T28	1		T46	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	29	1			T39	1		T40	2		T41	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T41	1		T23	1		T205	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T17	1		T18	1		T28	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	395	1			T17	1		T18	1		T28	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T28	1		T46	1		T42	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T47	1		T49	1		T85	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T28	1		T39	1		T46	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T40	1		T185	1		T89	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T28	1		T39	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T41	1		T253	2		T270	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T202	2		T200	1		T268	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T47	1		T89	1		T184	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T12	2		T28	8		T39	4
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T12	2		T28	2		T39	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T28	1		T39	2		T253	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T47	1		T22	2		T253	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T197	1		T205	2		T202	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T47	1		T185	2		T205	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T28	1		T39	2		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T22	1		T42	1		T49	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T40	1		T253	2		T202	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T253	2		T23	1		T199	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T15	1		T19	1		T28	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	352	1			T15	1		T19	1		T28	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T28	1		T46	1		T217	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T28	1		T22	1		T85	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T217	1		T198	1		T268	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T22	1		T185	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T40	1		T202	1		T200	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T28	1		T39	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T85	1		T197	1		T202	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T39	1		T42	1		T85	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	328	1			T12	1		T19	1		T28	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T12	1		T19	1		T28	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T39	2		T40	1		T22	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T22	1		T23	2		T202	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T28	1		T39	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T185	1		T202	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T39	1		T22	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	43	1			T49	1		T85	2		T218	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T39	1		T42	1		T247	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T40	1		T200	1		T83	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	355	1			T28	5		T39	3		T40	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T28	1		T39	1		T47	4