Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4875	1			T17	18		T19	14		T28	20
values[1]	3953	1			T28	23		T39	159		T46	103
values[2]	3915	1			T12	12		T28	41		T40	63
values[3]	4194	1			T3	12		T28	25		T39	147
values[4]	4229	1			T18	26		T28	84		T52	10
values[5]	3226	1			T28	23		T39	83		T46	20
values[6]	4017	1			T28	62		T39	20		T129	22
values[7]	4116	1			T15	13		T28	20		T39	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4140	1			T15	13		T28	40		T39	132
values[1]	3386	1			T28	25		T46	21		T258	2
values[2]	4136	1			T12	12		T28	41		T39	83
values[3]	4119	1			T28	43		T129	22		T40	40
values[4]	4206	1			T19	14		T28	42		T39	20
values[5]	3807	1			T3	12		T18	26		T28	63
values[6]	4904	1			T17	18		T28	44		T46	103
values[7]	3827	1			T39	112		T46	20		T40	29

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31622

1

T3

12

T12

12

T15

13

auto[1]

903

1

T28

7

T39

6

T50

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	532	1			T28	20		T85	31		T197	20
auto[0]	values[0]	values[1]	478	1			T93	12		T42	19		T175	16
auto[0]	values[0]	values[2]	495	1			T253	12		T49	20		T85	26
auto[0]	values[0]	values[3]	919	1			T22	18		T197	19		T202	24
auto[0]	values[0]	values[4]	460	1			T19	14		T39	19		T185	40
auto[0]	values[0]	values[5]	515	1			T205	26		T83	18		T237	20
auto[0]	values[0]	values[6]	729	1			T17	18		T22	20		T220	10
auto[0]	values[0]	values[7]	611	1			T22	20		T186	22		T185	20
auto[0]	values[1]	values[0]	493	1			T40	49		T226	58		T83	14
auto[0]	values[1]	values[1]	332	1			T22	35		T23	21		T277	14
auto[0]	values[1]	values[2]	576	1			T259	4		T23	46		T183	22
auto[0]	values[1]	values[3]	318	1			T147	16		T185	30		T202	20
auto[0]	values[1]	values[4]	514	1			T40	24		T185	68		T205	79
auto[0]	values[1]	values[5]	508	1			T39	102		T205	20		T226	23
auto[0]	values[1]	values[6]	668	1			T28	21		T46	103		T233	8
auto[0]	values[1]	values[7]	426	1			T39	57		T40	24		T22	20
auto[0]	values[2]	values[0]	470	1			T202	20		T33	135		T237	21
auto[0]	values[2]	values[1]	299	1			T40	20		T42	19		T49	19
auto[0]	values[2]	values[2]	707	1			T12	12		T28	21		T47	79
auto[0]	values[2]	values[3]	289	1			T96	20		T278	24		T279	20
auto[0]	values[2]	values[4]	384	1			T22	20		T235	6		T218	20
auto[0]	values[2]	values[5]	487	1			T28	20		T185	20		T205	54
auto[0]	values[2]	values[6]	719	1			T40	41		T47	51		T267	4
auto[0]	values[2]	values[7]	465	1			T23	19		T42	41		T254	2
auto[0]	values[3]	values[0]	396	1			T39	89		T50	19		T85	26
auto[0]	values[3]	values[1]	298	1			T28	24		T258	2		T47	31
auto[0]	values[3]	values[2]	271	1			T250	4		T200	19		T83	20
auto[0]	values[3]	values[3]	620	1			T40	18		T185	70		T217	25
auto[0]	values[3]	values[4]	851	1			T47	20		T42	20		T185	130
auto[0]	values[3]	values[5]	532	1			T3	12		T101	8		T85	24
auto[0]	values[3]	values[6]	592	1			T94	10		T49	19		T33	18
auto[0]	values[3]	values[7]	517	1			T39	54		T23	20		T244	20
auto[0]	values[4]	values[0]	403	1			T28	20		T52	10		T40	18
auto[0]	values[4]	values[1]	709	1			T46	20		T40	20		T271	4
auto[0]	values[4]	values[2]	553	1			T218	29		T83	19		T270	20
auto[0]	values[4]	values[3]	456	1			T28	21		T280	12		T33	37
auto[0]	values[4]	values[4]	752	1			T28	41		T49	40		T217	22
auto[0]	values[4]	values[5]	394	1			T18	26		T243	6		T251	4
auto[0]	values[4]	values[6]	358	1			T42	20		T229	14		T270	20
auto[0]	values[4]	values[7]	500	1			T46	20		T202	18		T217	20
auto[0]	values[5]	values[0]	413	1			T39	20		T46	19		T261	18
auto[0]	values[5]	values[1]	382	1			T23	39		T265	8		T184	24
auto[0]	values[5]	values[2]	386	1			T39	62		T23	26		T217	25
auto[0]	values[5]	values[3]	430	1			T245	2		T281	4		T89	19
auto[0]	values[5]	values[4]	397	1			T219	8		T85	23		T202	28
auto[0]	values[5]	values[5]	416	1			T28	23		T41	8		T23	19
auto[0]	values[5]	values[6]	475	1			T47	38		T22	23		T83	39
auto[0]	values[5]	values[7]	240	1			T208	2		T185	22		T197	39
auto[0]	values[6]	values[0]	476	1			T39	20		T197	19		T89	17
auto[0]	values[6]	values[1]	367	1			T42	19		T217	20		T215	43
auto[0]	values[6]	values[2]	361	1			T282	4		T23	89		T234	10
auto[0]	values[6]	values[3]	452	1			T28	21		T129	22		T150	14
auto[0]	values[6]	values[4]	435	1			T40	20		T49	22		T217	20
auto[0]	values[6]	values[5]	612	1			T28	20		T48	10		T49	21
auto[0]	values[6]	values[6]	640	1			T28	19		T85	19		T227	14
auto[0]	values[6]	values[7]	556	1			T185	40		T202	42		T89	19
auto[0]	values[7]	values[0]	839	1			T15	13		T23	23		T185	49
auto[0]	values[7]	values[1]	428	1			T256	4		T197	18		T205	89
auto[0]	values[7]	values[2]	675	1			T28	20		T39	20		T249	18
auto[0]	values[7]	values[3]	521	1			T40	17		T197	20		T89	19
auto[0]	values[7]	values[4]	276	1			T283	12		T218	20		T284	18
auto[0]	values[7]	values[5]	251	1			T252	4		T200	21		T237	20
auto[0]	values[7]	values[6]	593	1			T47	28		T201	26		T197	20
auto[0]	values[7]	values[7]	405	1			T22	20		T218	57		T200	51
auto[1]	values[0]	values[0]	10	1			T85	1		T231	2		T285	2
auto[1]	values[0]	values[1]	14	1			T42	1		T49	1		T226	1
auto[1]	values[0]	values[2]	11	1			T85	1		T89	1		T263	1
auto[1]	values[0]	values[3]	28	1			T22	3		T197	1		T202	3
auto[1]	values[0]	values[4]	17	1			T39	1		T85	1		T214	2
auto[1]	values[0]	values[5]	21	1			T205	1		T83	2		T242	1
auto[1]	values[0]	values[6]	17	1			T42	1		T226	1		T89	1
auto[1]	values[0]	values[7]	18	1			T242	1		T198	1		T151	3
auto[1]	values[1]	values[0]	19	1			T40	1		T226	2		T83	6
auto[1]	values[1]	values[1]	16	1			T22	3		T200	1		T96	1
auto[1]	values[1]	values[2]	17	1			T23	1		T183	1		T237	3
auto[1]	values[1]	values[3]	6	1			T264	3		T286	3		-	-
auto[1]	values[1]	values[4]	13	1			T185	2		T200	2		T287	2
auto[1]	values[1]	values[5]	11	1			T200	1		T33	2		T211	2
auto[1]	values[1]	values[6]	18	1			T28	2		T233	4		T214	4
auto[1]	values[1]	values[7]	18	1			T40	5		T288	2		T184	4
auto[1]	values[2]	values[0]	16	1			T33	3		T237	1		T289	6
auto[1]	values[2]	values[1]	11	1			T42	1		T49	2		T198	1
auto[1]	values[2]	values[2]	14	1			T47	1		T42	1		T199	1
auto[1]	values[2]	values[3]	5	1			T290	5		-	-		-	-
auto[1]	values[2]	values[4]	10	1			T22	2		T33	1		T151	1
auto[1]	values[2]	values[5]	5	1			T89	1		T222	2		T98	1
auto[1]	values[2]	values[6]	21	1			T40	2		T47	3		T202	1
auto[1]	values[2]	values[7]	13	1			T23	1		T42	1		T200	1
auto[1]	values[3]	values[0]	9	1			T39	3		T50	1		T85	1
auto[1]	values[3]	values[1]	8	1			T28	1		T47	1		T205	1
auto[1]	values[3]	values[2]	8	1			T200	1		T198	3		T268	2
auto[1]	values[3]	values[3]	17	1			T40	2		T185	2		T215	1
auto[1]	values[3]	values[4]	26	1			T185	2		T85	4		T96	5
auto[1]	values[3]	values[5]	12	1			T85	1		T291	2		T247	1
auto[1]	values[3]	values[6]	14	1			T49	1		T33	2		T292	1
auto[1]	values[3]	values[7]	23	1			T39	1		T85	1		T205	1
auto[1]	values[4]	values[0]	6	1			T40	2		T33	1		T151	1
auto[1]	values[4]	values[1]	8	1			T46	1		T197	2		T242	1
auto[1]	values[4]	values[2]	23	1			T218	1		T83	1		T270	1
auto[1]	values[4]	values[3]	17	1			T28	1		T184	1		T152	2
auto[1]	values[4]	values[4]	24	1			T28	1		T49	1		T200	1
auto[1]	values[4]	values[5]	6	1			T292	2		T206	3		T285	1
auto[1]	values[4]	values[6]	11	1			T270	2		T290	1		T293	4
auto[1]	values[4]	values[7]	9	1			T202	2		T215	1		T255	2
auto[1]	values[5]	values[0]	13	1			T46	1		T198	1		T98	4
auto[1]	values[5]	values[1]	6	1			T23	1		T184	1		T222	2
auto[1]	values[5]	values[2]	10	1			T39	1		T268	2		T151	1
auto[1]	values[5]	values[3]	17	1			T89	1		T198	2		T292	1
auto[1]	values[5]	values[4]	14	1			T85	4		T202	1		T287	1
auto[1]	values[5]	values[5]	6	1			T23	1		T294	2		T295	3
auto[1]	values[5]	values[6]	17	1			T47	2		T22	1		T83	1
auto[1]	values[5]	values[7]	4	1			T197	1		T296	2		T297	1
auto[1]	values[6]	values[0]	20	1			T197	1		T89	3		T198	1
auto[1]	values[6]	values[1]	9	1			T42	1		T215	1		T231	1
auto[1]	values[6]	values[2]	9	1			T23	3		T202	2		T298	1
auto[1]	values[6]	values[3]	11	1			T299	4		T246	3		T297	1
auto[1]	values[6]	values[4]	13	1			T89	1		T300	1		T268	3
auto[1]	values[6]	values[5]	23	1			T48	4		T205	1		T211	1
auto[1]	values[6]	values[6]	17	1			T28	2		T85	1		T202	2
auto[1]	values[6]	values[7]	16	1			T89	1		T199	2		T198	5
auto[1]	values[7]	values[0]	25	1			T23	1		T185	1		T214	2
auto[1]	values[7]	values[1]	21	1			T197	2		T205	7		T248	1
auto[1]	values[7]	values[2]	20	1			T218	2		T298	2		T173	1
auto[1]	values[7]	values[3]	13	1			T40	3		T89	1		T199	2
auto[1]	values[7]	values[4]	20	1			T242	2		T255	1		T152	4
auto[1]	values[7]	values[5]	8	1			T200	1		T301	2		T264	2
auto[1]	values[7]	values[6]	15	1			T205	3		T246	3		T206	1
auto[1]	values[7]	values[7]	6	1			T200	2		T270	1		T212	1