Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	691	1			T24	10		T30	7		T31	4
all_values[1]	691	1			T24	10		T30	7		T31	4
all_values[2]	691	1			T24	10		T30	7		T31	4
all_values[3]	691	1			T24	10		T30	7		T31	4
all_values[4]	691	1			T24	10		T30	7		T31	4
all_values[5]	691	1			T24	10		T30	7		T31	4
all_values[6]	691	1			T24	10		T30	7		T31	4
all_values[7]	691	1			T24	10		T30	7		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2898

1

T24

30

T30

26

T31

12

auto[1]

2630

1

T24

50

T30

30

T31

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2218

1

T24

27

T30

16

T31

11

auto[1]

3310

1

T24

53

T30

40

T31

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3196

1

T24

41

T30

25

T31

18

auto[1]

2332

1

T24

39

T30

31

T31

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	125	1			T24	1		T30	2		T31	1
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T24	2		T31	1		T183	2
all_values[0]	auto[0]	auto[1]	auto[0]	123	1			T24	3		T30	2		T32	7
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T24	1		T31	1		T32	1
all_values[0]	auto[1]	auto[0]	auto[1]	160	1			T24	1		T30	2		T31	1
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T24	2		T30	1		T32	5
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T30	1		T31	1		T183	1
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T24	1		T30	1		T183	1
all_values[1]	auto[0]	auto[1]	auto[0]	119	1			T24	1		T31	1		T32	6
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T24	1		T30	1		T31	1
all_values[1]	auto[1]	auto[0]	auto[1]	146	1			T24	2		T30	2		T183	1
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T24	5		T30	2		T31	1
all_values[2]	auto[0]	auto[0]	auto[0]	121	1			T24	1		T30	1		T183	1
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T30	1		T31	1		T32	4
all_values[2]	auto[0]	auto[1]	auto[0]	118	1			T24	3		T30	2		T32	3
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T24	1		T32	3		T33	1
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T24	1		T31	1		T183	1
all_values[2]	auto[1]	auto[1]	auto[1]	129	1			T24	4		T30	3		T31	2
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T24	2		T31	1		T183	1
all_values[3]	auto[0]	auto[0]	auto[1]	63	1			T31	1		T32	2		T169	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T24	5		T31	1		T183	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T24	1		T30	1		T32	1
all_values[3]	auto[1]	auto[0]	auto[1]	154	1			T24	1		T30	2		T31	1
all_values[3]	auto[1]	auto[1]	auto[1]	125	1			T24	1		T30	4		T183	1
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T24	2		T30	1		T32	5
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T24	1		T30	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	114	1			T24	2		T30	1		T31	2
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T30	1		T31	1		T183	2
all_values[4]	auto[1]	auto[0]	auto[1]	146	1			T24	4		T30	2		T32	8
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T24	1		T30	1		T31	1
all_values[5]	auto[0]	auto[0]	auto[0]	214	1			T24	1		T30	1		T183	1
all_values[5]	auto[0]	auto[1]	auto[0]	176	1			T24	1		T30	2		T31	2
all_values[5]	auto[1]	auto[0]	auto[1]	168	1			T24	4		T30	2		T183	2
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T24	4		T30	2		T31	2
all_values[6]	auto[0]	auto[0]	auto[0]	114	1			T24	3		T30	1		T183	2
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T30	1		T32	4		T184	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T24	1		T183	1		T32	2
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T24	4		T30	1		T31	1
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T24	2		T30	1		T31	1
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T30	3		T31	2		T32	7
all_values[7]	auto[0]	auto[0]	auto[0]	154	1			T30	2		T32	5		T33	3
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T30	1		T32	4		T184	2
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T24	1		T31	2		T183	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T24	2		T32	4		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	142	1			T24	1		T30	1		T31	2
all_values[7]	auto[1]	auto[1]	auto[1]	126	1			T24	6		T30	3		T183	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal