Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733

1

T9

2

T11

6

T27

9

auto[1]

1720

1

T9

4

T11

4

T25

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T11

10

T25

1

T28

13

auto[1]

1537

1

T9

6

T27

14

T29

18

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2750

1

T9

6

T11

4

T25

1

auto[1]

703

1

T11

6

T28

2

T55

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	665	1			T9	1		T11	1		T28	1
valid[1]	715	1			T9	1		T11	3		T27	2
valid[2]	663	1			T9	1		T11	5		T25	1
valid[3]	714	1			T9	3		T27	7		T28	3
valid[4]	696	1			T11	1		T27	3		T28	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T11	1		T56	1		T72	4
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T54	2		T90	1		T91	5
auto[0]	auto[0]	valid[1]	auto[0]	118	1			T28	1		T56	1		T22	1
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T29	4		T310	1		T315	6
auto[0]	auto[0]	valid[2]	auto[0]	112	1			T11	2		T71	1		T72	2
auto[0]	auto[0]	valid[2]	auto[1]	139	1			T9	1		T27	2		T29	3
auto[0]	auto[0]	valid[3]	auto[0]	153	1			T28	1		T55	1		T56	4
auto[0]	auto[0]	valid[3]	auto[1]	148	1			T9	1		T27	5		T29	1
auto[0]	auto[0]	valid[4]	auto[0]	127	1			T28	1		T56	1		T57	2
auto[0]	auto[0]	valid[4]	auto[1]	152	1			T27	2		T29	1		T90	1
auto[0]	auto[1]	valid[0]	auto[0]	105	1			T28	1		T56	1		T72	1
auto[0]	auto[1]	valid[0]	auto[1]	153	1			T9	1		T90	2		T327	2
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T11	1		T28	2		T72	5
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T9	1		T27	2		T29	3
auto[0]	auto[1]	valid[2]	auto[0]	116	1			T25	1		T28	1		T55	2
auto[0]	auto[1]	valid[2]	auto[1]	148	1			T29	2		T54	1		T56	1
auto[0]	auto[1]	valid[3]	auto[0]	130	1			T28	1		T57	2		T71	1
auto[0]	auto[1]	valid[3]	auto[1]	160	1			T9	2		T27	2		T29	2
auto[0]	auto[1]	valid[4]	auto[0]	104	1			T28	3		T72	1		T40	2
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T27	1		T29	2		T56	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T55	1		T56	1		T57	2
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T11	2		T28	1		T56	1
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T11	1		T40	1		T310	1
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T28	1		T40	3		T22	1
auto[1]	auto[0]	valid[4]	auto[0]	84	1			T72	2		T323	1		T23	1
auto[1]	auto[1]	valid[0]	auto[0]	59	1			T187	1		T310	1		T311	1
auto[1]	auto[1]	valid[1]	auto[0]	80	1			T56	1		T72	1		T40	1
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T11	2		T56	2		T71	1
auto[1]	auto[1]	valid[3]	auto[0]	58	1			T56	1		T57	1		T71	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T11	1		T57	2		T40	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal