Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50401

1

T5

2

T10

4

T11

187

auto[1]

15574

1

T9

6

T11

25

T27

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47665

1

T5

2

T9

6

T10

4

auto[1]

18310

1

T11

75

T13

3

T25

8

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34016	1			T5	1		T9	6		T10	1
others[1]	5483	1			T11	13		T13	2		T25	5
others[2]	5614	1			T5	1		T10	1		T11	23
others[3]	6291	1			T11	24		T25	3		T28	49
interest[1]	3629	1			T11	13		T25	3		T28	30
interest[4]	22247	1			T5	1		T9	6		T10	1
interest[64]	10942	1			T10	2		T11	28		T25	6

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16507	1			T5	1		T10	1		T11	57
auto[0]	auto[0]	others[1]	2686	1			T11	7		T13	1		T25	3
auto[0]	auto[0]	others[2]	2771	1			T5	1		T10	1		T11	16
auto[0]	auto[0]	others[3]	3079	1			T11	15		T25	3		T28	27
auto[0]	auto[0]	interest[1]	1718	1			T11	6		T25	3		T28	23
auto[0]	auto[0]	interest[4]	10811	1			T5	1		T10	1		T11	34
auto[0]	auto[0]	interest[64]	5330	1			T10	2		T11	11		T25	6
auto[0]	auto[1]	others[0]	8079	1			T9	6		T11	13		T27	14
auto[0]	auto[1]	others[1]	1245	1			T11	1		T29	14		T55	2
auto[0]	auto[1]	others[2]	1310	1			T11	1		T29	23		T55	2
auto[0]	auto[1]	others[3]	1455	1			T11	3		T29	21		T55	4
auto[0]	auto[1]	interest[1]	906	1			T11	3		T29	5		T55	1
auto[0]	auto[1]	interest[4]	5294	1			T9	6		T11	8		T27	14
auto[0]	auto[1]	interest[64]	2579	1			T11	4		T29	37		T55	4
auto[1]	auto[0]	others[0]	9430	1			T11	41		T13	2		T25	5
auto[1]	auto[0]	others[1]	1552	1			T11	5		T13	1		T25	2
auto[1]	auto[0]	others[2]	1533	1			T11	6		T25	1		T26	1
auto[1]	auto[0]	others[3]	1757	1			T11	6		T28	22		T55	1
auto[1]	auto[0]	interest[1]	1005	1			T11	4		T28	7		T55	4
auto[1]	auto[0]	interest[4]	6142	1			T11	24		T13	2		T25	3
auto[1]	auto[0]	interest[64]	3033	1			T11	13		T28	29		T55	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal