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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T1040 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1641435669 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 14152158 ps
T134 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.885976576 Aug 19 05:08:36 PM PDT 24 Aug 19 05:08:39 PM PDT 24 162232897 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.985602216 Aug 19 05:08:21 PM PDT 24 Aug 19 05:08:24 PM PDT 24 154094283 ps
T135 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2257486877 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:41 PM PDT 24 135536060 ps
T1041 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3625187628 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:41 PM PDT 24 72201600 ps
T1042 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3046398875 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:44 PM PDT 24 172260920 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4264993637 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:41 PM PDT 24 43441395 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1195883654 Aug 19 05:08:14 PM PDT 24 Aug 19 05:08:30 PM PDT 24 2507865558 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3765432828 Aug 19 05:08:14 PM PDT 24 Aug 19 05:08:22 PM PDT 24 1194653063 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2183055598 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:28 PM PDT 24 174222820 ps
T137 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3260359853 Aug 19 05:08:37 PM PDT 24 Aug 19 05:08:40 PM PDT 24 185209428 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.152944576 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:27 PM PDT 24 13935854 ps
T1046 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4167104959 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 16051764 ps
T1047 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.856388086 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:44 PM PDT 24 36812052 ps
T1048 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4051984325 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:41 PM PDT 24 17793047 ps
T138 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2872401597 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:36 PM PDT 24 867673556 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3504871514 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:17 PM PDT 24 47760985 ps
T164 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4085228401 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:36 PM PDT 24 690943970 ps
T127 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.376187082 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:41 PM PDT 24 74181970 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2668686329 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:40 PM PDT 24 19999198 ps
T165 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2852393401 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:31 PM PDT 24 503740849 ps
T1051 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2537055490 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:43 PM PDT 24 16393555 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.586699245 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:17 PM PDT 24 116224159 ps
T1053 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1070427139 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:39 PM PDT 24 106415469 ps
T166 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.981355989 Aug 19 05:08:29 PM PDT 24 Aug 19 05:09:07 PM PDT 24 46881522376 ps
T1054 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4088505389 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 190273645 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4263641331 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:17 PM PDT 24 18983727 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.474645566 Aug 19 05:08:15 PM PDT 24 Aug 19 05:08:23 PM PDT 24 1231124016 ps
T139 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3750946900 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:48 PM PDT 24 580435210 ps
T116 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2599375473 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:42 PM PDT 24 164984914 ps
T192 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3225449205 Aug 19 05:08:15 PM PDT 24 Aug 19 05:08:24 PM PDT 24 1162055052 ps
T1057 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2568215374 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 95974785 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2104169737 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:47 PM PDT 24 560734133 ps
T140 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2429126596 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:29 PM PDT 24 246756143 ps
T114 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1824115495 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:49 PM PDT 24 1744606939 ps
T117 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.194400715 Aug 19 05:08:42 PM PDT 24 Aug 19 05:08:45 PM PDT 24 153217633 ps
T1058 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3152096192 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:26 PM PDT 24 21680898 ps
T167 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2100207628 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:19 PM PDT 24 2283217252 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3112006830 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:27 PM PDT 24 34487866 ps
T168 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1491075302 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:42 PM PDT 24 693485634 ps
T1060 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.671898522 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:42 PM PDT 24 76025316 ps
T115 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3457732815 Aug 19 05:08:15 PM PDT 24 Aug 19 05:08:19 PM PDT 24 425222808 ps
T1061 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1294801963 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:18 PM PDT 24 118425926 ps
T124 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.707773874 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:43 PM PDT 24 41570156 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1676001005 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:17 PM PDT 24 15739256 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1359112552 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:30 PM PDT 24 174795094 ps
T1064 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.857848734 Aug 19 05:08:37 PM PDT 24 Aug 19 05:08:38 PM PDT 24 20506882 ps
T1065 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3436263714 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 42868232 ps
T141 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1984792738 Aug 19 05:08:23 PM PDT 24 Aug 19 05:08:38 PM PDT 24 969057620 ps
T1066 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1605411757 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:48 PM PDT 24 119415988 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2698075384 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:47 PM PDT 24 139411940 ps
T1068 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3045696435 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 18872713 ps
T123 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1626896414 Aug 19 05:08:29 PM PDT 24 Aug 19 05:08:31 PM PDT 24 46746003 ps
T1069 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2748332737 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:46 PM PDT 24 85560076 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1648479661 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:42 PM PDT 24 39087091 ps
T119 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3506932752 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:42 PM PDT 24 127825006 ps
T1071 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2681081037 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:44 PM PDT 24 121680386 ps
T1072 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.675811304 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 13464880 ps
T1073 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4239569809 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:44 PM PDT 24 14345244 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4281667631 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:26 PM PDT 24 24762001 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3225149358 Aug 19 05:08:31 PM PDT 24 Aug 19 05:08:32 PM PDT 24 53921957 ps
T193 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3791194731 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:45 PM PDT 24 106065768 ps
T194 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2606582452 Aug 19 05:08:30 PM PDT 24 Aug 19 05:08:37 PM PDT 24 218273185 ps
T113 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.549446694 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:51 PM PDT 24 208012315 ps
T195 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.793150391 Aug 19 05:08:37 PM PDT 24 Aug 19 05:08:52 PM PDT 24 2291537099 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2468940879 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:41 PM PDT 24 18887004 ps
T1077 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4108097771 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 16276362 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3846033630 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:32 PM PDT 24 620397740 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3541333782 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:28 PM PDT 24 23527019 ps
T1080 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2523190531 Aug 19 05:08:42 PM PDT 24 Aug 19 05:08:43 PM PDT 24 15477763 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.713803724 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:28 PM PDT 24 23127973 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2228050025 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:47 PM PDT 24 292339159 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3401715009 Aug 19 05:08:29 PM PDT 24 Aug 19 05:08:30 PM PDT 24 38716554 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2759476492 Aug 19 05:08:38 PM PDT 24 Aug 19 05:09:01 PM PDT 24 3405891798 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.634553248 Aug 19 05:08:14 PM PDT 24 Aug 19 05:08:40 PM PDT 24 7188317179 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1035279595 Aug 19 05:08:20 PM PDT 24 Aug 19 05:08:22 PM PDT 24 40050227 ps
T1087 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3009745233 Aug 19 05:08:37 PM PDT 24 Aug 19 05:08:38 PM PDT 24 27804754 ps
T1088 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2885683484 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 12670084 ps
T112 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2845152743 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:50 PM PDT 24 191530224 ps
T1089 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.532313630 Aug 19 05:08:36 PM PDT 24 Aug 19 05:08:40 PM PDT 24 318687248 ps
T1090 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3730353287 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 31506856 ps
T1091 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2445004631 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:46 PM PDT 24 78767219 ps
T1092 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.266665032 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:45 PM PDT 24 64537279 ps
T1093 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.835106355 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:47 PM PDT 24 10822970 ps
T1094 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3269702931 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 48230585 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2923769329 Aug 19 05:08:17 PM PDT 24 Aug 19 05:08:21 PM PDT 24 600952850 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2513671261 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:44 PM PDT 24 446594761 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2273748753 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:29 PM PDT 24 62423930 ps
T1098 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.549743450 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:29 PM PDT 24 49151148 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1498639884 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:41 PM PDT 24 296163461 ps
T1100 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2312329556 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 14770670 ps
T1101 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3226294957 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 75331391 ps
T142 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.516789290 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:28 PM PDT 24 27058772 ps
T143 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1151911909 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:43 PM PDT 24 78740896 ps
T1102 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1042628923 Aug 19 05:08:36 PM PDT 24 Aug 19 05:08:37 PM PDT 24 17528911 ps
T1103 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2499472264 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:44 PM PDT 24 17225654 ps
T1104 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1399393378 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:39 PM PDT 24 54042078 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3237770599 Aug 19 05:08:25 PM PDT 24 Aug 19 05:08:27 PM PDT 24 35381021 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3482735824 Aug 19 05:08:28 PM PDT 24 Aug 19 05:09:05 PM PDT 24 4793684620 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.769082725 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:44 PM PDT 24 74181207 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.202650660 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:46 PM PDT 24 43203467 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1890950577 Aug 19 05:08:14 PM PDT 24 Aug 19 05:08:17 PM PDT 24 69472241 ps
T120 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.136875986 Aug 19 05:08:46 PM PDT 24 Aug 19 05:08:51 PM PDT 24 176077460 ps
T1109 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3509997083 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:47 PM PDT 24 69326206 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1891856090 Aug 19 05:08:14 PM PDT 24 Aug 19 05:08:15 PM PDT 24 36140559 ps
T1111 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3729759553 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:46 PM PDT 24 1942885905 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3627612747 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:30 PM PDT 24 83998848 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1397644940 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:42 PM PDT 24 2616642351 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3382518399 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:29 PM PDT 24 21641229 ps
T196 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.735030983 Aug 19 05:08:32 PM PDT 24 Aug 19 05:08:40 PM PDT 24 283828221 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4068935566 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:30 PM PDT 24 61909296 ps
T86 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1825903556 Aug 19 05:08:32 PM PDT 24 Aug 19 05:08:33 PM PDT 24 81157232 ps
T1116 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1404651231 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:42 PM PDT 24 149945041 ps
T191 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1969871817 Aug 19 05:08:36 PM PDT 24 Aug 19 05:08:43 PM PDT 24 4363477752 ps
T1117 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.941300344 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:43 PM PDT 24 277936399 ps
T1118 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.823808464 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:44 PM PDT 24 50015010 ps
T1119 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.37639598 Aug 19 05:08:31 PM PDT 24 Aug 19 05:08:34 PM PDT 24 170168397 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2759747304 Aug 19 05:08:21 PM PDT 24 Aug 19 05:08:24 PM PDT 24 97513865 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3576609004 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:42 PM PDT 24 11354311 ps
T1122 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1232391269 Aug 19 05:08:45 PM PDT 24 Aug 19 05:08:46 PM PDT 24 12821301 ps
T1123 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1525614036 Aug 19 05:08:42 PM PDT 24 Aug 19 05:08:43 PM PDT 24 40633684 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3600956148 Aug 19 05:08:29 PM PDT 24 Aug 19 05:08:30 PM PDT 24 691956252 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3467939476 Aug 19 05:08:15 PM PDT 24 Aug 19 05:08:46 PM PDT 24 6494175283 ps
T1126 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3618731031 Aug 19 05:08:38 PM PDT 24 Aug 19 05:08:39 PM PDT 24 15611332 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.67749553 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:40 PM PDT 24 60951155 ps
T87 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4068733716 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:28 PM PDT 24 33199939 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1175043825 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:31 PM PDT 24 265484571 ps
T1129 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1970235227 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:41 PM PDT 24 46223007 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2389256862 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:49 PM PDT 24 1350645242 ps
T1131 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.70004464 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:47 PM PDT 24 1548893517 ps
T1132 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.902395537 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:41 PM PDT 24 147832414 ps
T88 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1709094824 Aug 19 05:08:16 PM PDT 24 Aug 19 05:08:17 PM PDT 24 559983485 ps
T1133 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.422207987 Aug 19 05:08:20 PM PDT 24 Aug 19 05:08:21 PM PDT 24 11828958 ps
T1134 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2528671341 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:29 PM PDT 24 361908702 ps
T1135 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2855919461 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 108000823 ps
T1136 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2088675040 Aug 19 05:08:41 PM PDT 24 Aug 19 05:08:44 PM PDT 24 96200216 ps
T1137 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4275726151 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:32 PM PDT 24 62608511 ps
T1138 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2919506402 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:46 PM PDT 24 241991380 ps
T1139 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1062207836 Aug 19 05:08:39 PM PDT 24 Aug 19 05:08:41 PM PDT 24 112587569 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3141515594 Aug 19 05:08:15 PM PDT 24 Aug 19 05:08:16 PM PDT 24 81568775 ps
T1141 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3120668110 Aug 19 05:08:26 PM PDT 24 Aug 19 05:08:28 PM PDT 24 99125000 ps
T1142 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1116800899 Aug 19 05:08:28 PM PDT 24 Aug 19 05:08:29 PM PDT 24 185462060 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3696643129 Aug 19 05:08:18 PM PDT 24 Aug 19 05:08:20 PM PDT 24 45711203 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2053853903 Aug 19 05:08:19 PM PDT 24 Aug 19 05:08:19 PM PDT 24 14489040 ps
T1145 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1111641658 Aug 19 05:08:43 PM PDT 24 Aug 19 05:08:44 PM PDT 24 12161197 ps
T1146 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.923900652 Aug 19 05:08:13 PM PDT 24 Aug 19 05:08:30 PM PDT 24 2914271848 ps
T1147 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.826105446 Aug 19 05:08:20 PM PDT 24 Aug 19 05:08:21 PM PDT 24 119775773 ps
T1148 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1224743408 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 69950270 ps
T1149 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3764627902 Aug 19 05:08:40 PM PDT 24 Aug 19 05:08:41 PM PDT 24 23706883 ps
T1150 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1385090145 Aug 19 05:08:27 PM PDT 24 Aug 19 05:08:30 PM PDT 24 132449510 ps
T1151 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.366127511 Aug 19 05:08:44 PM PDT 24 Aug 19 05:08:45 PM PDT 24 29668755 ps

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3130178026
Short name T4
Test name
Test status
Simulation time 22819547229 ps
CPU time 84.84 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:05:17 PM PDT 24
Peak memory 248932 kb
Host smart-8ec0c362-408f-490d-a636-e26c22d8ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130178026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3130178026
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1925076238
Short name T28
Test name
Test status
Simulation time 75543914608 ps
CPU time 702.1 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:15:36 PM PDT 24
Peak memory 269888 kb
Host smart-fe5c69b5-2cd5-4921-9911-e94b16ca9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925076238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1925076238
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.477290682
Short name T22
Test name
Test status
Simulation time 152046385421 ps
CPU time 218.19 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:05:58 PM PDT 24
Peak memory 250092 kb
Host smart-93cfa913-2c02-461c-9f9c-e75655e27b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477290682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.477290682
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2133681750
Short name T33
Test name
Test status
Simulation time 19818667417 ps
CPU time 120 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:04:39 PM PDT 24
Peak memory 257560 kb
Host smart-139a3a66-0c59-4365-a134-85299257335a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133681750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2133681750
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3791758892
Short name T107
Test name
Test status
Simulation time 933135216 ps
CPU time 22.23 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:59 PM PDT 24
Peak memory 216072 kb
Host smart-8aa1c609-533c-4ec0-9ed2-5e42ccea74d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791758892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3791758892
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3659604019
Short name T55
Test name
Test status
Simulation time 12044225970 ps
CPU time 53.26 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:05:47 PM PDT 24
Peak memory 256060 kb
Host smart-b19dfe95-c8bf-46ba-bcfe-aca44babcc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659604019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3659604019
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1707733598
Short name T77
Test name
Test status
Simulation time 16034804 ps
CPU time 0.74 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 216204 kb
Host smart-36beb59f-1053-4ce1-9816-3da1863aa4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707733598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1707733598
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2233135818
Short name T85
Test name
Test status
Simulation time 111840389074 ps
CPU time 544.1 seconds
Started Aug 19 06:02:35 PM PDT 24
Finished Aug 19 06:11:39 PM PDT 24
Peak memory 267768 kb
Host smart-960fcef4-67c7-4719-9e66-2fd8c64060cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233135818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2233135818
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.108060771
Short name T198
Test name
Test status
Simulation time 250170435265 ps
CPU time 477.57 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:10:39 PM PDT 24
Peak memory 282172 kb
Host smart-5f18a646-ccd4-4a68-905b-3494597b7256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108060771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.108060771
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1233758659
Short name T40
Test name
Test status
Simulation time 98608342824 ps
CPU time 511.86 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:12:13 PM PDT 24
Peak memory 265060 kb
Host smart-1d4731fa-ca60-462d-94cf-2e854bd5daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233758659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1233758659
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1139014262
Short name T217
Test name
Test status
Simulation time 59154526471 ps
CPU time 298.15 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:09:23 PM PDT 24
Peak memory 268620 kb
Host smart-fca9d3a2-7361-4aeb-bba4-12d1217d3217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139014262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1139014262
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.80013433
Short name T103
Test name
Test status
Simulation time 781738738 ps
CPU time 6.04 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 216120 kb
Host smart-35dd6a12-d99d-40a9-b9ee-5cc6de5aaf3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80013433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.80013433
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3438607360
Short name T45
Test name
Test status
Simulation time 8981727147 ps
CPU time 25.23 seconds
Started Aug 19 06:04:19 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 232952 kb
Host smart-183a7695-f712-4c48-9608-ea7bca576a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438607360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3438607360
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1342087187
Short name T6
Test name
Test status
Simulation time 62335902 ps
CPU time 1.04 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 235656 kb
Host smart-85555282-8360-4acb-bf0e-3184e117e08d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342087187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1342087187
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3325429160
Short name T202
Test name
Test status
Simulation time 6385098559 ps
CPU time 159.3 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:06:32 PM PDT 24
Peak memory 273716 kb
Host smart-14b7879f-9a98-4289-bdc4-a33ac3b32bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325429160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3325429160
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.93928450
Short name T200
Test name
Test status
Simulation time 152151260021 ps
CPU time 437.6 seconds
Started Aug 19 06:03:48 PM PDT 24
Finished Aug 19 06:11:06 PM PDT 24
Peak memory 273972 kb
Host smart-1811560b-34eb-4420-ad9c-40880baa0bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93928450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.93928450
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.73298056
Short name T31
Test name
Test status
Simulation time 22891378118 ps
CPU time 205.47 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 257332 kb
Host smart-6b434059-ef11-4771-b9b6-8f4181a695ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73298056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.73298056
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1195883654
Short name T136
Test name
Test status
Simulation time 2507865558 ps
CPU time 15.3 seconds
Started Aug 19 05:08:14 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 216092 kb
Host smart-f3c8b48e-e068-48ed-af45-37e739b4a93d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195883654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1195883654
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1600670437
Short name T205
Test name
Test status
Simulation time 11235009206 ps
CPU time 163.82 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:06:52 PM PDT 24
Peak memory 269144 kb
Host smart-ff38f5c5-5b51-4a26-aa48-7dfa52780416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600670437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1600670437
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.573687553
Short name T346
Test name
Test status
Simulation time 141557589 ps
CPU time 1.15 seconds
Started Aug 19 06:03:02 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 216724 kb
Host smart-dbe637ba-670e-48e1-96e0-e5f9e3e2f593
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573687553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.573687553
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3141577204
Short name T23
Test name
Test status
Simulation time 8353019675 ps
CPU time 104.87 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:04:18 PM PDT 24
Peak memory 250400 kb
Host smart-4cba3939-4bc1-4339-8661-44805f0bd122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141577204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3141577204
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3244782841
Short name T185
Test name
Test status
Simulation time 7049126100 ps
CPU time 119.32 seconds
Started Aug 19 06:02:16 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 273944 kb
Host smart-9bd8f8c7-80d7-4819-aa37-1d95bee6744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244782841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3244782841
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.943731203
Short name T297
Test name
Test status
Simulation time 50292799913 ps
CPU time 300.5 seconds
Started Aug 19 06:02:59 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 283320 kb
Host smart-f63bca45-dba9-4b40-b5bc-858ff059925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943731203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.943731203
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1783032190
Short name T29
Test name
Test status
Simulation time 14717846398 ps
CPU time 8.34 seconds
Started Aug 19 06:01:58 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 216556 kb
Host smart-d3b5cb5a-f5b7-4849-8a03-1d649817c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783032190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1783032190
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2190703307
Short name T216
Test name
Test status
Simulation time 457241232717 ps
CPU time 653.11 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:14:09 PM PDT 24
Peak memory 266836 kb
Host smart-48c263dd-8b32-4da8-997e-8e9e96784679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190703307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2190703307
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.507116966
Short name T34
Test name
Test status
Simulation time 55478623524 ps
CPU time 100.67 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 257576 kb
Host smart-00024d97-c06e-47c0-bbca-dd41d27f11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507116966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.507116966
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2557841277
Short name T184
Test name
Test status
Simulation time 154359226727 ps
CPU time 276.47 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:09:20 PM PDT 24
Peak memory 253400 kb
Host smart-34d714f2-1466-433b-8405-aaab85ff7d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557841277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2557841277
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1681203400
Short name T75
Test name
Test status
Simulation time 29748766 ps
CPU time 0.74 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 205564 kb
Host smart-f1b45e7f-8041-498d-a4f7-253fb3b27f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681203400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1681203400
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1440454127
Short name T290
Test name
Test status
Simulation time 28492304884 ps
CPU time 241.31 seconds
Started Aug 19 06:01:50 PM PDT 24
Finished Aug 19 06:05:52 PM PDT 24
Peak memory 255384 kb
Host smart-d2613bdf-4572-41ce-8538-fb6c6f1ea57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440454127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1440454127
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3997265814
Short name T98
Test name
Test status
Simulation time 22606758749 ps
CPU time 113.09 seconds
Started Aug 19 06:03:23 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 270472 kb
Host smart-52252732-831a-47d5-9293-f173766e469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997265814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3997265814
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.15210507
Short name T307
Test name
Test status
Simulation time 13941696750 ps
CPU time 58.24 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 224736 kb
Host smart-2c0a0519-33f8-4733-beb1-a8f0eb905810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15210507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.15210507
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1131373624
Short name T11
Test name
Test status
Simulation time 64593096347 ps
CPU time 103.25 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 252252 kb
Host smart-4ad1b57a-9ec8-4a30-bb80-6bca8447b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131373624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1131373624
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1979837243
Short name T197
Test name
Test status
Simulation time 10447629362 ps
CPU time 78.7 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 261936 kb
Host smart-bd8b34ce-044f-45a8-9cfb-369372e895b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979837243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1979837243
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2064748166
Short name T18
Test name
Test status
Simulation time 2884522449 ps
CPU time 5.06 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:22 PM PDT 24
Peak memory 232936 kb
Host smart-45ec47e3-a121-41e7-90b8-f81560f00d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064748166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2064748166
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.815782499
Short name T59
Test name
Test status
Simulation time 45272784450 ps
CPU time 204.63 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:07:08 PM PDT 24
Peak memory 249384 kb
Host smart-91107a80-56e4-4e0b-a731-c250c294401b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815782499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.815782499
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2919506402
Short name T1138
Test name
Test status
Simulation time 241991380 ps
CPU time 5.69 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 216060 kb
Host smart-10933587-2aa7-4b19-a2be-ca1d01d5bcfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919506402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2919506402
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3225449205
Short name T192
Test name
Test status
Simulation time 1162055052 ps
CPU time 8.81 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:24 PM PDT 24
Peak memory 216224 kb
Host smart-1fa4731c-c7c0-4b68-ba20-79b2dbbf0db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225449205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3225449205
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.735030983
Short name T196
Test name
Test status
Simulation time 283828221 ps
CPU time 7.66 seconds
Started Aug 19 05:08:32 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 216036 kb
Host smart-1ab13dbd-aca4-4bc1-874e-aefb8b8a15ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735030983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.735030983
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1033267522
Short name T351
Test name
Test status
Simulation time 4206565191 ps
CPU time 15.44 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 216552 kb
Host smart-4913d40c-1df3-401a-85e4-138405763df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033267522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1033267522
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1858437911
Short name T173
Test name
Test status
Simulation time 88661408284 ps
CPU time 332.48 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:08:40 PM PDT 24
Peak memory 257572 kb
Host smart-e9a73a09-d79b-473e-b926-b67cea182f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858437911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1858437911
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2866559288
Short name T35
Test name
Test status
Simulation time 32642749309 ps
CPU time 410.15 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 274164 kb
Host smart-e619dcc0-df53-4788-84a1-a83a295907a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866559288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2866559288
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1599960759
Short name T994
Test name
Test status
Simulation time 170925569242 ps
CPU time 823.74 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:17:10 PM PDT 24
Peak memory 282120 kb
Host smart-71ff36d0-85c7-437c-b605-7488527e877a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599960759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1599960759
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2922169027
Short name T94
Test name
Test status
Simulation time 681303171 ps
CPU time 12.9 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 224744 kb
Host smart-c85ab48a-8880-4631-b99c-a6e638e2b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922169027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2922169027
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3092965263
Short name T966
Test name
Test status
Simulation time 11496331461 ps
CPU time 178.97 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 265804 kb
Host smart-d698c939-87b7-4372-9085-e17e28159c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092965263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3092965263
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3309933272
Short name T240
Test name
Test status
Simulation time 23808260529 ps
CPU time 203.59 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:05:19 PM PDT 24
Peak memory 273848 kb
Host smart-e8d58680-a6c2-4a3f-a4ea-abb8bdb00d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309933272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3309933272
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1633748007
Short name T305
Test name
Test status
Simulation time 508771174 ps
CPU time 6.84 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:49 PM PDT 24
Peak memory 241048 kb
Host smart-a33dbab0-72c5-42de-9d8a-e1d7f4cff462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633748007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1633748007
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3992435363
Short name T292
Test name
Test status
Simulation time 2161832925 ps
CPU time 46.01 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:04:03 PM PDT 24
Peak memory 241696 kb
Host smart-21a02f6e-ae0a-4388-b149-398c63be43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992435363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3992435363
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2985848030
Short name T286
Test name
Test status
Simulation time 21617338230 ps
CPU time 177.74 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 270536 kb
Host smart-2f361ed9-3759-406f-9e38-b1170252e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985848030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2985848030
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.654886542
Short name T932
Test name
Test status
Simulation time 52784621802 ps
CPU time 134.68 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:05:57 PM PDT 24
Peak memory 256580 kb
Host smart-543e21ea-8ee0-4277-a3dc-895e862ac0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654886542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.654886542
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4075824999
Short name T255
Test name
Test status
Simulation time 4133677581 ps
CPU time 51.29 seconds
Started Aug 19 06:03:56 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 239844 kb
Host smart-02659896-94b3-400c-83eb-26cc459a84f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075824999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4075824999
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.604540485
Short name T89
Test name
Test status
Simulation time 114565538390 ps
CPU time 396.4 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:10:35 PM PDT 24
Peak memory 262584 kb
Host smart-1d544ef9-242f-4026-8c04-0b33eff20170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604540485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.604540485
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1709094824
Short name T88
Test name
Test status
Simulation time 559983485 ps
CPU time 1.23 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 207716 kb
Host smart-00d6873c-a8b1-4716-af6a-b59eecc4f786
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709094824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1709094824
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.167326535
Short name T106
Test name
Test status
Simulation time 2154607648 ps
CPU time 13.49 seconds
Started Aug 19 05:08:35 PM PDT 24
Finished Aug 19 05:08:49 PM PDT 24
Peak memory 216128 kb
Host smart-46326df7-bbf1-4eef-8f54-cddeec8d18c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167326535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.167326535
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1763556816
Short name T332
Test name
Test status
Simulation time 17018130 ps
CPU time 0.76 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 205600 kb
Host smart-9889836d-2657-441c-bf87-f1788b13156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763556816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1763556816
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.474645566
Short name T1056
Test name
Test status
Simulation time 1231124016 ps
CPU time 7.94 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:23 PM PDT 24
Peak memory 207732 kb
Host smart-2ab55971-d556-43a4-adcb-8a0178a469b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474645566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.474645566
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1984792738
Short name T141
Test name
Test status
Simulation time 969057620 ps
CPU time 14.53 seconds
Started Aug 19 05:08:23 PM PDT 24
Finished Aug 19 05:08:38 PM PDT 24
Peak memory 207636 kb
Host smart-a4c8d149-002e-4ec5-9838-fa0ad0b45886
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984792738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1984792738
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.826105446
Short name T1147
Test name
Test status
Simulation time 119775773 ps
CPU time 1.15 seconds
Started Aug 19 05:08:20 PM PDT 24
Finished Aug 19 05:08:21 PM PDT 24
Peak memory 207668 kb
Host smart-6ff0ff8b-b49e-446f-8dc4-a2e435903371
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826105446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.826105446
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1035279595
Short name T1086
Test name
Test status
Simulation time 40050227 ps
CPU time 1.59 seconds
Started Aug 19 05:08:20 PM PDT 24
Finished Aug 19 05:08:22 PM PDT 24
Peak memory 216004 kb
Host smart-b7c39d9b-40cf-4466-a54c-3d6a1c2ff2cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035279595 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1035279595
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.586699245
Short name T1052
Test name
Test status
Simulation time 116224159 ps
CPU time 1.36 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 207688 kb
Host smart-b514fd60-445e-4e2a-8c72-6c11a249c4fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586699245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.586699245
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1676001005
Short name T1062
Test name
Test status
Simulation time 15739256 ps
CPU time 0.73 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 204380 kb
Host smart-219f03de-a3b4-4bfb-a58a-ce04153fa3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676001005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
676001005
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1735287849
Short name T132
Test name
Test status
Simulation time 71341780 ps
CPU time 2.2 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:18 PM PDT 24
Peak memory 216012 kb
Host smart-accfd07f-ff7a-413e-a70f-8a90aa339a48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735287849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1735287849
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4263641331
Short name T1055
Test name
Test status
Simulation time 18983727 ps
CPU time 0.69 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 204332 kb
Host smart-bc8eaa15-5f18-4f59-8273-1f7d7cd31ca4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263641331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4263641331
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1294801963
Short name T1061
Test name
Test status
Simulation time 118425926 ps
CPU time 1.92 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:18 PM PDT 24
Peak memory 207796 kb
Host smart-7e566482-adaf-4cad-88de-06fb6b65af53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294801963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1294801963
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3457732815
Short name T115
Test name
Test status
Simulation time 425222808 ps
CPU time 3.13 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:19 PM PDT 24
Peak memory 216156 kb
Host smart-d9613585-eb27-41c6-b9d6-70898bdf4050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457732815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
457732815
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3467939476
Short name T1125
Test name
Test status
Simulation time 6494175283 ps
CPU time 30.97 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 215944 kb
Host smart-3f349c3e-d567-44c3-88ec-75ca1b008892
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467939476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3467939476
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2923769329
Short name T1095
Test name
Test status
Simulation time 600952850 ps
CPU time 3.71 seconds
Started Aug 19 05:08:17 PM PDT 24
Finished Aug 19 05:08:21 PM PDT 24
Peak memory 218528 kb
Host smart-649688b6-e14f-4630-8c28-89b92cc3880b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923769329 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2923769329
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2891300289
Short name T155
Test name
Test status
Simulation time 117230113 ps
CPU time 2.09 seconds
Started Aug 19 05:08:20 PM PDT 24
Finished Aug 19 05:08:22 PM PDT 24
Peak memory 216004 kb
Host smart-04e51ba2-a4bd-4d06-a0b7-5129f804a3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891300289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
891300289
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.838157329
Short name T1037
Test name
Test status
Simulation time 11888877 ps
CPU time 0.76 seconds
Started Aug 19 05:08:20 PM PDT 24
Finished Aug 19 05:08:21 PM PDT 24
Peak memory 204328 kb
Host smart-d76a2a7a-24a2-4e50-939f-0a92c3ddb73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838157329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.838157329
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2759747304
Short name T1120
Test name
Test status
Simulation time 97513865 ps
CPU time 2.02 seconds
Started Aug 19 05:08:21 PM PDT 24
Finished Aug 19 05:08:24 PM PDT 24
Peak memory 215872 kb
Host smart-99348445-c4a3-416b-b211-76f788f7aa40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759747304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2759747304
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.422207987
Short name T1133
Test name
Test status
Simulation time 11828958 ps
CPU time 0.66 seconds
Started Aug 19 05:08:20 PM PDT 24
Finished Aug 19 05:08:21 PM PDT 24
Peak memory 204316 kb
Host smart-349e418c-4be9-4087-8da6-c1a6f209dc78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422207987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.422207987
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2100207628
Short name T167
Test name
Test status
Simulation time 2283217252 ps
CPU time 3.11 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:19 PM PDT 24
Peak memory 216016 kb
Host smart-b51c3a14-ca00-4cd9-9136-0d341bff276d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100207628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2100207628
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1582437964
Short name T109
Test name
Test status
Simulation time 37517676 ps
CPU time 2.26 seconds
Started Aug 19 05:08:21 PM PDT 24
Finished Aug 19 05:08:23 PM PDT 24
Peak memory 216104 kb
Host smart-b77acaf9-5640-4b59-b443-52e6683e2f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582437964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
582437964
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3765432828
Short name T126
Test name
Test status
Simulation time 1194653063 ps
CPU time 7.41 seconds
Started Aug 19 05:08:14 PM PDT 24
Finished Aug 19 05:08:22 PM PDT 24
Peak memory 216212 kb
Host smart-04b40702-089d-4612-9099-8a79f8a8f0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765432828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3765432828
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.902395537
Short name T1132
Test name
Test status
Simulation time 147832414 ps
CPU time 1.79 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 216108 kb
Host smart-b710423a-b4d1-46d4-bd9a-4c2578f40fd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902395537 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.902395537
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3750946900
Short name T139
Test name
Test status
Simulation time 580435210 ps
CPU time 2.84 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:48 PM PDT 24
Peak memory 215904 kb
Host smart-cd6f98d0-41b1-4b80-b678-9b3204e78af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750946900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3750946900
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3618731031
Short name T1126
Test name
Test status
Simulation time 15611332 ps
CPU time 0.74 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:39 PM PDT 24
Peak memory 204344 kb
Host smart-49825281-3688-428d-98b5-1e8753e95290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618731031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3618731031
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1491075302
Short name T168
Test name
Test status
Simulation time 693485634 ps
CPU time 3.05 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 215932 kb
Host smart-3d09de7b-671f-4611-b613-0e7b8ca98a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491075302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1491075302
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.532313630
Short name T1089
Test name
Test status
Simulation time 318687248 ps
CPU time 3.33 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 217148 kb
Host smart-86f77903-efd2-4edb-a7fa-24b754df4293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532313630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.532313630
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2228050025
Short name T1082
Test name
Test status
Simulation time 292339159 ps
CPU time 7.72 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 215928 kb
Host smart-0fae2ac2-9f9b-4ddb-bebe-7ded83c163f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228050025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2228050025
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2698075384
Short name T1067
Test name
Test status
Simulation time 139411940 ps
CPU time 1.85 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 217096 kb
Host smart-055fcd2a-7cbb-49fe-8051-b4cd842649e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698075384 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2698075384
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1151911909
Short name T143
Test name
Test status
Simulation time 78740896 ps
CPU time 2.1 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 207820 kb
Host smart-52f042a6-311e-4554-bf4c-36fa9533483a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151911909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1151911909
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4051984325
Short name T1048
Test name
Test status
Simulation time 17793047 ps
CPU time 0.77 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 204344 kb
Host smart-ddc7bd86-617d-4314-8c5e-f32a422789ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051984325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4051984325
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2513671261
Short name T1096
Test name
Test status
Simulation time 446594761 ps
CPU time 3.05 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 215936 kb
Host smart-f7cdff23-5530-4f95-9e89-779fa5c16100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513671261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2513671261
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2088675040
Short name T1136
Test name
Test status
Simulation time 96200216 ps
CPU time 2.66 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 217464 kb
Host smart-8d5378e1-2cf6-4651-8646-65bdac43c22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088675040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2088675040
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.823808464
Short name T1118
Test name
Test status
Simulation time 50015010 ps
CPU time 1.77 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 215984 kb
Host smart-d56cd77f-ed81-4296-877f-4e6b4b75f5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823808464 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.823808464
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3509997083
Short name T1109
Test name
Test status
Simulation time 69326206 ps
CPU time 2.11 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 207820 kb
Host smart-0fdd4e24-7e55-4fdb-ad19-54bc6969145e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509997083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3509997083
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2468940879
Short name T1076
Test name
Test status
Simulation time 18887004 ps
CPU time 0.79 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 204356 kb
Host smart-ff037860-07de-4ced-8a53-28e11d26a512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468940879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2468940879
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.769082725
Short name T1106
Test name
Test status
Simulation time 74181207 ps
CPU time 3.99 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 215932 kb
Host smart-307c413a-8cb6-4aeb-a6bd-f55cdc49aa19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769082725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.769082725
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1969871817
Short name T191
Test name
Test status
Simulation time 4363477752 ps
CPU time 6.79 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 216280 kb
Host smart-23c3a985-18ca-42e5-8239-488883ce80e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969871817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1969871817
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.793150391
Short name T195
Test name
Test status
Simulation time 2291537099 ps
CPU time 15.18 seconds
Started Aug 19 05:08:37 PM PDT 24
Finished Aug 19 05:08:52 PM PDT 24
Peak memory 216052 kb
Host smart-f8963d7c-5450-4a18-940c-6466eea2aafb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793150391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.793150391
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3506932752
Short name T119
Test name
Test status
Simulation time 127825006 ps
CPU time 3.7 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 217812 kb
Host smart-fcd06c4c-1136-4204-a701-e77eeff634c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506932752 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3506932752
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3625187628
Short name T1041
Test name
Test status
Simulation time 72201600 ps
CPU time 2.1 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 216000 kb
Host smart-2794a1f7-913a-4d94-8aca-d68273b04040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625187628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3625187628
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1648479661
Short name T1070
Test name
Test status
Simulation time 39087091 ps
CPU time 0.75 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 204572 kb
Host smart-623759cf-836a-4033-83e7-7f24e27ec581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648479661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1648479661
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1498639884
Short name T1099
Test name
Test status
Simulation time 296163461 ps
CPU time 3.28 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 216016 kb
Host smart-42110181-640b-4e16-be7f-2d857613664c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498639884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1498639884
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3729759553
Short name T1111
Test name
Test status
Simulation time 1942885905 ps
CPU time 8.06 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 215788 kb
Host smart-77198088-f021-4071-b93a-28ca40573418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729759553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3729759553
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2445004631
Short name T1091
Test name
Test status
Simulation time 78767219 ps
CPU time 2.56 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 217212 kb
Host smart-7d9453fa-6b6e-44cf-8984-94666266ecf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445004631 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2445004631
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.885976576
Short name T134
Test name
Test status
Simulation time 162232897 ps
CPU time 2.54 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:39 PM PDT 24
Peak memory 207776 kb
Host smart-00cf7928-761c-4c2f-a4b5-14ef790d61a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885976576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.885976576
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1042628923
Short name T1102
Test name
Test status
Simulation time 17528911 ps
CPU time 0.76 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:37 PM PDT 24
Peak memory 204308 kb
Host smart-44479b5d-ddf4-4138-94a5-c4b19806b542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042628923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1042628923
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1873644994
Short name T156
Test name
Test status
Simulation time 142683426 ps
CPU time 2.03 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 215992 kb
Host smart-a8ee2de4-ef9a-46f6-97f3-9eb976d2ffb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873644994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1873644994
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2759476492
Short name T1084
Test name
Test status
Simulation time 3405891798 ps
CPU time 22.84 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:09:01 PM PDT 24
Peak memory 216592 kb
Host smart-975e7d92-6cc4-4690-a511-9436ea64126b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759476492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2759476492
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.202650660
Short name T1107
Test name
Test status
Simulation time 43203467 ps
CPU time 2.63 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 218272 kb
Host smart-6be93e2a-1a6a-4637-a08a-8dcd5f96f3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202650660 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.202650660
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.67749553
Short name T1127
Test name
Test status
Simulation time 60951155 ps
CPU time 1.29 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 215920 kb
Host smart-29c436d5-5921-4e1f-b2ac-3f7c75d1672c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67749553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.67749553
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1399393378
Short name T1104
Test name
Test status
Simulation time 54042078 ps
CPU time 0.76 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:39 PM PDT 24
Peak memory 204356 kb
Host smart-9b53345f-9ba4-4a66-8f0c-290dd599ac26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399393378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1399393378
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2681081037
Short name T1071
Test name
Test status
Simulation time 121680386 ps
CPU time 3.8 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 215968 kb
Host smart-a8b29a71-9ed6-4a5d-817f-aae769be90c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681081037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2681081037
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2845152743
Short name T112
Test name
Test status
Simulation time 191530224 ps
CPU time 4.55 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:50 PM PDT 24
Peak memory 216144 kb
Host smart-a2c19f35-7f78-49a9-ac25-cb2e85d48684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845152743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2845152743
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3791194731
Short name T193
Test name
Test status
Simulation time 106065768 ps
CPU time 7.07 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 215864 kb
Host smart-073a6c6a-f91f-4ba4-ae20-3fb84fce25d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791194731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3791194731
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2748332737
Short name T1069
Test name
Test status
Simulation time 85560076 ps
CPU time 1.73 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 215996 kb
Host smart-f6bb969a-3298-4f28-b8f8-e7a34059a3ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748332737 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2748332737
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2257486877
Short name T135
Test name
Test status
Simulation time 135536060 ps
CPU time 1.25 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 207728 kb
Host smart-0b963d73-c3a4-470c-8dce-6e5c8a6985f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257486877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2257486877
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1224743408
Short name T1148
Test name
Test status
Simulation time 69950270 ps
CPU time 0.79 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204368 kb
Host smart-3a5af776-c8dd-46b0-b6ea-4d11dcb0b3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224743408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1224743408
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3046398875
Short name T1042
Test name
Test status
Simulation time 172260920 ps
CPU time 4.19 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 216424 kb
Host smart-ba29532e-ca3d-4c9c-ab84-bfb50c9c121f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046398875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3046398875
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2599375473
Short name T116
Test name
Test status
Simulation time 164984914 ps
CPU time 2.21 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 216156 kb
Host smart-fef6dc04-9006-405b-b0be-88b9160377de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599375473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2599375473
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3782683144
Short name T125
Test name
Test status
Simulation time 409608588 ps
CPU time 6.67 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 215940 kb
Host smart-3c518c77-5452-4025-8615-9300662cc1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782683144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3782683144
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1605411757
Short name T1066
Test name
Test status
Simulation time 119415988 ps
CPU time 3.16 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:48 PM PDT 24
Peak memory 217680 kb
Host smart-aecc0039-ac1e-42e3-9c9d-d6441e1a7e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605411757 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1605411757
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3260359853
Short name T137
Test name
Test status
Simulation time 185209428 ps
CPU time 2.58 seconds
Started Aug 19 05:08:37 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 215932 kb
Host smart-d20b379e-1d37-4720-b66d-7e2f7e85d0ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260359853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3260359853
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.857848734
Short name T1064
Test name
Test status
Simulation time 20506882 ps
CPU time 0.77 seconds
Started Aug 19 05:08:37 PM PDT 24
Finished Aug 19 05:08:38 PM PDT 24
Peak memory 204308 kb
Host smart-ba9575f9-b2d4-4e9a-ad06-571a47354c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857848734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.857848734
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2855919461
Short name T1135
Test name
Test status
Simulation time 108000823 ps
CPU time 1.79 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 207716 kb
Host smart-6ecef587-9ec7-42ba-ada6-446c456d141a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855919461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2855919461
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.549446694
Short name T113
Test name
Test status
Simulation time 208012315 ps
CPU time 5.11 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:51 PM PDT 24
Peak memory 216212 kb
Host smart-fb77507e-23a1-4a05-b2fc-5ebef7004f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549446694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.549446694
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.266665032
Short name T1092
Test name
Test status
Simulation time 64537279 ps
CPU time 3.94 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 218376 kb
Host smart-72ad848e-d890-47f0-b89b-05b0b84af200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266665032 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.266665032
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2086429398
Short name T131
Test name
Test status
Simulation time 412396812 ps
CPU time 2.65 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 216012 kb
Host smart-1524d8b9-d3eb-40a8-89fa-d76d0786dee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086429398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2086429398
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3576609004
Short name T1121
Test name
Test status
Simulation time 11354311 ps
CPU time 0.75 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 204404 kb
Host smart-439a691d-e9fd-471d-a5d9-e78c1e5e5370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576609004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3576609004
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1062207836
Short name T1139
Test name
Test status
Simulation time 112587569 ps
CPU time 1.74 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 215996 kb
Host smart-60b00e11-55c5-4830-b41f-4b0cacb7f3d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062207836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1062207836
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.194400715
Short name T117
Test name
Test status
Simulation time 153217633 ps
CPU time 2.38 seconds
Started Aug 19 05:08:42 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 217152 kb
Host smart-08dca395-bfa9-4f27-8868-bb5c7f2820d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194400715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.194400715
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2483000930
Short name T105
Test name
Test status
Simulation time 1090308465 ps
CPU time 7.09 seconds
Started Aug 19 05:08:36 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 215892 kb
Host smart-cc70d4e3-b84a-459f-aa98-a14efb2b2f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483000930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2483000930
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.707773874
Short name T124
Test name
Test status
Simulation time 41570156 ps
CPU time 2.8 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 217860 kb
Host smart-71d3fa62-1afe-4ad2-8a5a-04f8caa30bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707773874 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.707773874
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1992368513
Short name T133
Test name
Test status
Simulation time 37258225 ps
CPU time 2.39 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 215932 kb
Host smart-12f55d14-7b88-472f-b1ff-ee72e15de075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992368513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1992368513
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4264993637
Short name T1043
Test name
Test status
Simulation time 43441395 ps
CPU time 0.71 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 204680 kb
Host smart-eadc8220-9bb2-4c70-97d8-cb4eba2f2e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264993637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4264993637
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.941300344
Short name T1117
Test name
Test status
Simulation time 277936399 ps
CPU time 3.69 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 215928 kb
Host smart-d11efc61-b283-426a-a4c5-5bde5a844bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941300344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.941300344
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.136875986
Short name T120
Test name
Test status
Simulation time 176077460 ps
CPU time 4.87 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:51 PM PDT 24
Peak memory 216148 kb
Host smart-bf274662-1bf7-409b-84d7-3a69bf11ff0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136875986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.136875986
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.70004464
Short name T1131
Test name
Test status
Simulation time 1548893517 ps
CPU time 7.6 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 216052 kb
Host smart-f91a96f8-ba0c-4b67-a3e8-20b5d1b7244c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70004464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_
tl_intg_err.70004464
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3914879045
Short name T1035
Test name
Test status
Simulation time 458728349 ps
CPU time 7.72 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:24 PM PDT 24
Peak memory 216052 kb
Host smart-225901df-b43a-4067-95bf-e58f01963607
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914879045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3914879045
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.634553248
Short name T1085
Test name
Test status
Simulation time 7188317179 ps
CPU time 25.59 seconds
Started Aug 19 05:08:14 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 207776 kb
Host smart-3e99426d-26f1-4f43-b771-0c7f8c21ee8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634553248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.634553248
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.492682335
Short name T130
Test name
Test status
Simulation time 116713252 ps
CPU time 1.23 seconds
Started Aug 19 05:08:17 PM PDT 24
Finished Aug 19 05:08:18 PM PDT 24
Peak memory 216956 kb
Host smart-c990d21a-d28d-4758-95b0-45124f041a7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492682335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.492682335
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2918858598
Short name T102
Test name
Test status
Simulation time 313109285 ps
CPU time 3.88 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:19 PM PDT 24
Peak memory 217788 kb
Host smart-450af711-179d-4933-ae77-4284eef6b4ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918858598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2918858598
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3141515594
Short name T1140
Test name
Test status
Simulation time 81568775 ps
CPU time 1.38 seconds
Started Aug 19 05:08:15 PM PDT 24
Finished Aug 19 05:08:16 PM PDT 24
Peak memory 216004 kb
Host smart-9083fd72-2562-44d2-b0c8-e82d54bfdf68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141515594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
141515594
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1891856090
Short name T1110
Test name
Test status
Simulation time 36140559 ps
CPU time 0.79 seconds
Started Aug 19 05:08:14 PM PDT 24
Finished Aug 19 05:08:15 PM PDT 24
Peak memory 204348 kb
Host smart-227668be-1b66-421a-8e7d-dd25226785a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891856090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
891856090
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3696643129
Short name T1143
Test name
Test status
Simulation time 45711203 ps
CPU time 1.82 seconds
Started Aug 19 05:08:18 PM PDT 24
Finished Aug 19 05:08:20 PM PDT 24
Peak memory 215936 kb
Host smart-a7d66c81-d534-43ba-b617-502747e2ccbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696643129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3696643129
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2053853903
Short name T1144
Test name
Test status
Simulation time 14489040 ps
CPU time 0.67 seconds
Started Aug 19 05:08:19 PM PDT 24
Finished Aug 19 05:08:19 PM PDT 24
Peak memory 204672 kb
Host smart-fa8bfb3e-5565-4819-ae2c-ebe463068e18
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053853903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2053853903
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2183055598
Short name T1044
Test name
Test status
Simulation time 174222820 ps
CPU time 2.7 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 215988 kb
Host smart-82b2047e-02d5-48e2-bd0f-16762d76b315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183055598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2183055598
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3237770599
Short name T121
Test name
Test status
Simulation time 35381021 ps
CPU time 2.2 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:27 PM PDT 24
Peak memory 216060 kb
Host smart-fcef599f-66e1-4ae2-9e5b-c61ab5427ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237770599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
237770599
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.923900652
Short name T1146
Test name
Test status
Simulation time 2914271848 ps
CPU time 16.29 seconds
Started Aug 19 05:08:13 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 217536 kb
Host smart-ab9568db-60dd-4694-8e76-bd8015127809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923900652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.923900652
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3730353287
Short name T1090
Test name
Test status
Simulation time 31506856 ps
CPU time 0.81 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204664 kb
Host smart-0da2946d-0edc-4a03-88e8-e2fa85c2979f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730353287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3730353287
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3269702931
Short name T1094
Test name
Test status
Simulation time 48230585 ps
CPU time 0.74 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204684 kb
Host smart-f1069aed-a063-4f7b-a635-19e1c524e981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269702931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3269702931
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1641435669
Short name T1040
Test name
Test status
Simulation time 14152158 ps
CPU time 0.78 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204348 kb
Host smart-f4747e34-a5f3-43e8-a0ae-9cb5f512490f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641435669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1641435669
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1232391269
Short name T1122
Test name
Test status
Simulation time 12821301 ps
CPU time 0.75 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204360 kb
Host smart-ff72d58d-39da-4945-ad60-761f4761c401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232391269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1232391269
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1111641658
Short name T1145
Test name
Test status
Simulation time 12161197 ps
CPU time 0.79 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 204484 kb
Host smart-5c7216f7-524e-4aea-92fc-80834be61976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111641658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1111641658
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3009745233
Short name T1087
Test name
Test status
Simulation time 27804754 ps
CPU time 0.72 seconds
Started Aug 19 05:08:37 PM PDT 24
Finished Aug 19 05:08:38 PM PDT 24
Peak memory 204624 kb
Host smart-df00e6f2-31c3-453a-8d83-8d752a939a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009745233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3009745233
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4167104959
Short name T1046
Test name
Test status
Simulation time 16051764 ps
CPU time 0.76 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204348 kb
Host smart-9d9e2c3e-741e-418f-9d86-f11a36a93add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167104959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4167104959
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3764627902
Short name T1149
Test name
Test status
Simulation time 23706883 ps
CPU time 0.73 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 204376 kb
Host smart-faa117d4-864a-4753-8160-da6976aab2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764627902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3764627902
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4108097771
Short name T1077
Test name
Test status
Simulation time 16276362 ps
CPU time 0.78 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204680 kb
Host smart-dd615df3-9423-4ef1-8b1c-ae9777480312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108097771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4108097771
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4239569809
Short name T1073
Test name
Test status
Simulation time 14345244 ps
CPU time 0.73 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 204688 kb
Host smart-fd55ed20-d6f5-4b5c-b7db-b6a5156e36fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239569809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4239569809
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2872401597
Short name T138
Test name
Test status
Simulation time 867673556 ps
CPU time 9.04 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:36 PM PDT 24
Peak memory 207772 kb
Host smart-7bf848f7-da78-4311-a771-ac73f0138ec0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872401597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2872401597
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3482735824
Short name T1105
Test name
Test status
Simulation time 4793684620 ps
CPU time 36.77 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:09:05 PM PDT 24
Peak memory 207828 kb
Host smart-41f1b1d0-6734-4d7c-90a4-94b0bab57784
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482735824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3482735824
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1825903556
Short name T86
Test name
Test status
Simulation time 81157232 ps
CPU time 0.93 seconds
Started Aug 19 05:08:32 PM PDT 24
Finished Aug 19 05:08:33 PM PDT 24
Peak memory 207420 kb
Host smart-a49b4bdd-d6d3-4f4e-bb32-d8cabb287070
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825903556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1825903556
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3627612747
Short name T1112
Test name
Test status
Simulation time 83998848 ps
CPU time 2.82 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 216968 kb
Host smart-b39b5c38-e815-4666-8560-327064f5c0b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627612747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3627612747
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3401715009
Short name T1083
Test name
Test status
Simulation time 38716554 ps
CPU time 1.35 seconds
Started Aug 19 05:08:29 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 215996 kb
Host smart-4dc19158-bee4-4a83-a6b4-2a25db74820b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401715009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
401715009
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3504871514
Short name T1049
Test name
Test status
Simulation time 47760985 ps
CPU time 0.74 seconds
Started Aug 19 05:08:16 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 204696 kb
Host smart-94ca838a-12cb-48ba-9c5c-103a536f8545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504871514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
504871514
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1890950577
Short name T1108
Test name
Test status
Simulation time 69472241 ps
CPU time 2.3 seconds
Started Aug 19 05:08:14 PM PDT 24
Finished Aug 19 05:08:17 PM PDT 24
Peak memory 215940 kb
Host smart-59fa4f18-3fff-498b-9c23-23af52841ca1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890950577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1890950577
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4281667631
Short name T1074
Test name
Test status
Simulation time 24762001 ps
CPU time 0.67 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:26 PM PDT 24
Peak memory 204320 kb
Host smart-eb6098de-4954-43ed-9493-d3bad11ed0c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281667631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4281667631
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4068935566
Short name T1115
Test name
Test status
Simulation time 61909296 ps
CPU time 1.74 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 215928 kb
Host smart-19116169-873a-4841-b1f8-da48216d78d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068935566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4068935566
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.985602216
Short name T110
Test name
Test status
Simulation time 154094283 ps
CPU time 2.93 seconds
Started Aug 19 05:08:21 PM PDT 24
Finished Aug 19 05:08:24 PM PDT 24
Peak memory 216000 kb
Host smart-5cf8af4f-3872-470e-937c-ffaa1c33ff68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985602216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.985602216
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3391831024
Short name T122
Test name
Test status
Simulation time 7486452072 ps
CPU time 21.96 seconds
Started Aug 19 05:08:19 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 216112 kb
Host smart-35db7d13-1e80-40de-9db7-22703930442f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391831024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3391831024
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1970235227
Short name T1129
Test name
Test status
Simulation time 46223007 ps
CPU time 0.77 seconds
Started Aug 19 05:08:40 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 204384 kb
Host smart-24151f04-8715-41bb-a5f9-682637992920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970235227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1970235227
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1070427139
Short name T1053
Test name
Test status
Simulation time 106415469 ps
CPU time 0.69 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:39 PM PDT 24
Peak memory 204360 kb
Host smart-97e990e4-633f-4777-a4de-48fce03c3195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070427139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1070427139
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.856388086
Short name T1047
Test name
Test status
Simulation time 36812052 ps
CPU time 0.73 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 204684 kb
Host smart-6ead97d4-ddb8-4741-a8fc-c13dcd692bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856388086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.856388086
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1525614036
Short name T1123
Test name
Test status
Simulation time 40633684 ps
CPU time 0.8 seconds
Started Aug 19 05:08:42 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 204248 kb
Host smart-507e541d-7b81-43ce-91bf-1f75d9893dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525614036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1525614036
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2499472264
Short name T1103
Test name
Test status
Simulation time 17225654 ps
CPU time 0.76 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:44 PM PDT 24
Peak memory 204172 kb
Host smart-d56c95c2-edbf-4b76-8af0-53e89c832a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499472264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2499472264
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3226294957
Short name T1101
Test name
Test status
Simulation time 75331391 ps
CPU time 0.76 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204380 kb
Host smart-bef34ef4-1a34-427f-b826-3d640239b64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226294957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3226294957
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2537055490
Short name T1051
Test name
Test status
Simulation time 16393555 ps
CPU time 0.73 seconds
Started Aug 19 05:08:43 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 204572 kb
Host smart-ee18443a-f10e-4ada-9309-2eb9a8ee8b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537055490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2537055490
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3425263800
Short name T1036
Test name
Test status
Simulation time 60776846 ps
CPU time 0.7 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204372 kb
Host smart-37208790-1db5-4be1-b143-1f2748dc539f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425263800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3425263800
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2885683484
Short name T1088
Test name
Test status
Simulation time 12670084 ps
CPU time 0.78 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204348 kb
Host smart-bd2beeb5-85f5-4dbe-9257-e6e8fa876677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885683484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2885683484
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3436263714
Short name T1065
Test name
Test status
Simulation time 42868232 ps
CPU time 0.76 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204364 kb
Host smart-891aed58-4756-4031-89d4-f8b811b244bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436263714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3436263714
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1397644940
Short name T1113
Test name
Test status
Simulation time 2616642351 ps
CPU time 15.05 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 216036 kb
Host smart-b1e40904-9d64-4e89-bede-531551481f12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397644940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1397644940
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.981355989
Short name T166
Test name
Test status
Simulation time 46881522376 ps
CPU time 37.22 seconds
Started Aug 19 05:08:29 PM PDT 24
Finished Aug 19 05:09:07 PM PDT 24
Peak memory 216012 kb
Host smart-8738d57a-e0b3-48a2-b8dd-c27f207a16cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981355989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.981355989
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4068733716
Short name T87
Test name
Test status
Simulation time 33199939 ps
CPU time 1.19 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 207736 kb
Host smart-0e6d9b29-ee0a-4377-8175-ae226f919666
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068733716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4068733716
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1175043825
Short name T1128
Test name
Test status
Simulation time 265484571 ps
CPU time 3.31 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:31 PM PDT 24
Peak memory 217872 kb
Host smart-8b4c22bc-87c6-46cc-a818-d9d59caef063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175043825 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1175043825
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3382518399
Short name T1114
Test name
Test status
Simulation time 21641229 ps
CPU time 1.37 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 207712 kb
Host smart-5d42a478-640d-474e-a323-7c60005a8b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382518399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
382518399
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.152944576
Short name T1045
Test name
Test status
Simulation time 13935854 ps
CPU time 0.71 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:27 PM PDT 24
Peak memory 204336 kb
Host smart-e4316bec-b2ab-42e6-8ef0-14d5bc3a8fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152944576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.152944576
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.516789290
Short name T142
Test name
Test status
Simulation time 27058772 ps
CPU time 2.59 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 216020 kb
Host smart-f044201c-721d-42b6-af76-39ae48f7d870
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516789290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.516789290
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3225149358
Short name T1075
Test name
Test status
Simulation time 53921957 ps
CPU time 0.71 seconds
Started Aug 19 05:08:31 PM PDT 24
Finished Aug 19 05:08:32 PM PDT 24
Peak memory 204280 kb
Host smart-af8ae601-c931-4449-a94f-9ed96fd52843
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225149358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3225149358
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3846033630
Short name T1078
Test name
Test status
Simulation time 620397740 ps
CPU time 3.93 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:32 PM PDT 24
Peak memory 216036 kb
Host smart-ed348617-84e8-4e51-90a7-a764569925a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846033630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3846033630
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3120668110
Short name T1141
Test name
Test status
Simulation time 99125000 ps
CPU time 2.51 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 216312 kb
Host smart-321bf857-6dcd-46b6-87b0-76609beb0bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120668110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
120668110
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2389256862
Short name T1130
Test name
Test status
Simulation time 1350645242 ps
CPU time 20.93 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:49 PM PDT 24
Peak memory 216456 kb
Host smart-79027ef0-75ee-4163-ae25-3b298093ddd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389256862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2389256862
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2523190531
Short name T1080
Test name
Test status
Simulation time 15477763 ps
CPU time 0.84 seconds
Started Aug 19 05:08:42 PM PDT 24
Finished Aug 19 05:08:43 PM PDT 24
Peak memory 204676 kb
Host smart-709f0bed-e3bc-46e0-bfa7-f7e64b57ba0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523190531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2523190531
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2312329556
Short name T1100
Test name
Test status
Simulation time 14770670 ps
CPU time 0.76 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204672 kb
Host smart-77dbef1a-530e-49e9-a590-4bcaa5a459a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312329556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2312329556
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3045696435
Short name T1068
Test name
Test status
Simulation time 18872713 ps
CPU time 0.78 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204696 kb
Host smart-f28be438-7f28-43f4-8bdb-f68756492c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045696435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3045696435
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3819928615
Short name T1038
Test name
Test status
Simulation time 22587324 ps
CPU time 0.84 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204372 kb
Host smart-d7c25c36-e1cd-4501-b27f-d4f6f2fc4d86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819928615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3819928615
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.675811304
Short name T1072
Test name
Test status
Simulation time 13464880 ps
CPU time 0.8 seconds
Started Aug 19 05:08:45 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 204376 kb
Host smart-e3fdcd3d-fb09-4cc0-9ee7-fbe046513b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675811304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.675811304
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.366127511
Short name T1151
Test name
Test status
Simulation time 29668755 ps
CPU time 0.7 seconds
Started Aug 19 05:08:44 PM PDT 24
Finished Aug 19 05:08:45 PM PDT 24
Peak memory 204352 kb
Host smart-b083cdd0-6090-4acc-adee-9d7e259b92d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366127511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.366127511
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4088505389
Short name T1054
Test name
Test status
Simulation time 190273645 ps
CPU time 0.76 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204352 kb
Host smart-ffe89835-9f6d-4e75-a82d-c13fa3286cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088505389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4088505389
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.835106355
Short name T1093
Test name
Test status
Simulation time 10822970 ps
CPU time 0.78 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204356 kb
Host smart-53c3b662-a4f2-40a0-9485-0421477f5f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835106355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.835106355
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.671898522
Short name T1060
Test name
Test status
Simulation time 76025316 ps
CPU time 0.71 seconds
Started Aug 19 05:08:41 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 204372 kb
Host smart-0e8facf0-4782-479c-9d85-d58e75b7c013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671898522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.671898522
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2568215374
Short name T1057
Test name
Test status
Simulation time 95974785 ps
CPU time 0.83 seconds
Started Aug 19 05:08:46 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 204380 kb
Host smart-20db6c54-3b79-45b2-8eea-bef38460421a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568215374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2568215374
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1626896414
Short name T123
Test name
Test status
Simulation time 46746003 ps
CPU time 1.68 seconds
Started Aug 19 05:08:29 PM PDT 24
Finished Aug 19 05:08:31 PM PDT 24
Peak memory 215932 kb
Host smart-36e3bbba-a442-4df4-b77a-f88285f926e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626896414 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1626896414
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1116800899
Short name T1142
Test name
Test status
Simulation time 185462060 ps
CPU time 1.41 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 216012 kb
Host smart-1e8f7a3f-78b5-40bb-823a-19c8c2436a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116800899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
116800899
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3152096192
Short name T1058
Test name
Test status
Simulation time 21680898 ps
CPU time 0.66 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:26 PM PDT 24
Peak memory 204308 kb
Host smart-6d1a8f6f-2042-4467-aed6-ad9e1b25b729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152096192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
152096192
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4275726151
Short name T1137
Test name
Test status
Simulation time 62608511 ps
CPU time 3.88 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:32 PM PDT 24
Peak memory 215900 kb
Host smart-51829218-7b8c-4d55-9054-9f4dfca22f65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275726151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4275726151
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.549743450
Short name T1098
Test name
Test status
Simulation time 49151148 ps
CPU time 2.52 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 216140 kb
Host smart-bf5ecc92-e7bb-4518-92ed-62a3b1e71e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549743450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.549743450
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4085228401
Short name T164
Test name
Test status
Simulation time 690943970 ps
CPU time 7.73 seconds
Started Aug 19 05:08:28 PM PDT 24
Finished Aug 19 05:08:36 PM PDT 24
Peak memory 215992 kb
Host smart-f3df0444-6706-45a3-9df0-f75bd67722d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085228401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4085228401
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1359112552
Short name T1063
Test name
Test status
Simulation time 174795094 ps
CPU time 2.92 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 217184 kb
Host smart-6080fcfe-a91c-4caf-883c-478ca3917077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359112552 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1359112552
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2429126596
Short name T140
Test name
Test status
Simulation time 246756143 ps
CPU time 2.23 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 215988 kb
Host smart-95260824-9d93-4c96-8cba-85df7ae9a43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429126596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
429126596
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3112006830
Short name T1059
Test name
Test status
Simulation time 34487866 ps
CPU time 0.73 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:27 PM PDT 24
Peak memory 204652 kb
Host smart-ad6cac3f-8bdf-4ee0-93be-78f44de5b4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112006830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
112006830
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2059954738
Short name T163
Test name
Test status
Simulation time 1136009839 ps
CPU time 3.15 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 215904 kb
Host smart-24e7cf04-359a-45d7-8aa6-6073bf3a121a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059954738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2059954738
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3600956148
Short name T1124
Test name
Test status
Simulation time 691956252 ps
CPU time 1.81 seconds
Started Aug 19 05:08:29 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 216168 kb
Host smart-3a9de289-c87c-40bc-85a5-5172b8f11bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600956148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
600956148
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1937838649
Short name T104
Test name
Test status
Simulation time 192244519 ps
CPU time 2.74 seconds
Started Aug 19 05:08:30 PM PDT 24
Finished Aug 19 05:08:33 PM PDT 24
Peak memory 217796 kb
Host smart-21975f31-0854-41e8-97cd-f06edbaed90a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937838649 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1937838649
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2528671341
Short name T1134
Test name
Test status
Simulation time 361908702 ps
CPU time 2.73 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 216016 kb
Host smart-c08f93e0-efbc-4f8a-bfc6-f42e0ea87723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528671341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
528671341
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.713803724
Short name T1081
Test name
Test status
Simulation time 23127973 ps
CPU time 0.74 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 204356 kb
Host smart-42e33a6f-5f44-4702-9e36-b1d15ea078a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713803724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.713803724
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2273748753
Short name T1097
Test name
Test status
Simulation time 62423930 ps
CPU time 4.06 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:29 PM PDT 24
Peak memory 215892 kb
Host smart-600b2206-ab37-46ca-9799-bdee7c8be259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273748753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2273748753
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.37639598
Short name T1119
Test name
Test status
Simulation time 170168397 ps
CPU time 2.33 seconds
Started Aug 19 05:08:31 PM PDT 24
Finished Aug 19 05:08:34 PM PDT 24
Peak memory 216156 kb
Host smart-9ad17c4e-db74-47b4-9644-3ec35a5a0edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.37639598
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2606582452
Short name T194
Test name
Test status
Simulation time 218273185 ps
CPU time 7 seconds
Started Aug 19 05:08:30 PM PDT 24
Finished Aug 19 05:08:37 PM PDT 24
Peak memory 216028 kb
Host smart-e2f05859-871a-4b6f-92ec-6d13355b4097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606582452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2606582452
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.376187082
Short name T127
Test name
Test status
Simulation time 74181970 ps
CPU time 2.82 seconds
Started Aug 19 05:08:38 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 217388 kb
Host smart-9c5c1341-8b1f-4515-820f-eb09e32e5c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376187082 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.376187082
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3541333782
Short name T1079
Test name
Test status
Simulation time 23527019 ps
CPU time 1.29 seconds
Started Aug 19 05:08:26 PM PDT 24
Finished Aug 19 05:08:28 PM PDT 24
Peak memory 207720 kb
Host smart-d0cd865f-7427-412d-a5d4-49c00d8c7cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541333782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
541333782
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2350557432
Short name T1034
Test name
Test status
Simulation time 19816612 ps
CPU time 0.74 seconds
Started Aug 19 05:08:29 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 204340 kb
Host smart-8dd343ee-854e-4951-85ab-74763f5071fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350557432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
350557432
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2852393401
Short name T165
Test name
Test status
Simulation time 503740849 ps
CPU time 4.63 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:31 PM PDT 24
Peak memory 215944 kb
Host smart-bea43a8b-e266-4a7c-aaad-b0b98e8fdc01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852393401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2852393401
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1385090145
Short name T1150
Test name
Test status
Simulation time 132449510 ps
CPU time 3.01 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 216180 kb
Host smart-3f28878d-3385-4442-8b9d-fcdf55862bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385090145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
385090145
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2104169737
Short name T118
Test name
Test status
Simulation time 560734133 ps
CPU time 19.33 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:47 PM PDT 24
Peak memory 216012 kb
Host smart-acc270fe-e0c6-4b84-b963-49de428c4254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104169737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2104169737
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.703065795
Short name T108
Test name
Test status
Simulation time 140634938 ps
CPU time 3.98 seconds
Started Aug 19 05:08:37 PM PDT 24
Finished Aug 19 05:08:41 PM PDT 24
Peak memory 217940 kb
Host smart-b3ebf200-aba4-40a6-be1f-e36e6fde14f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703065795 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.703065795
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1404651231
Short name T1116
Test name
Test status
Simulation time 149945041 ps
CPU time 2.5 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:42 PM PDT 24
Peak memory 215928 kb
Host smart-21510272-4aaf-4966-8e9e-3c0c98cadc9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404651231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
404651231
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2668686329
Short name T1050
Test name
Test status
Simulation time 19999198 ps
CPU time 0.7 seconds
Started Aug 19 05:08:39 PM PDT 24
Finished Aug 19 05:08:40 PM PDT 24
Peak memory 204316 kb
Host smart-4728739e-6930-4005-a89e-e25468eb1288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668686329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
668686329
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3903781792
Short name T1039
Test name
Test status
Simulation time 61820959 ps
CPU time 4.14 seconds
Started Aug 19 05:08:42 PM PDT 24
Finished Aug 19 05:08:46 PM PDT 24
Peak memory 215908 kb
Host smart-a17f5bd1-22fe-41ac-8083-3aa94502ea76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903781792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3903781792
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1733368478
Short name T111
Test name
Test status
Simulation time 195526107 ps
CPU time 2.67 seconds
Started Aug 19 05:08:27 PM PDT 24
Finished Aug 19 05:08:30 PM PDT 24
Peak memory 216072 kb
Host smart-b7237f03-467b-4b9a-9826-fe91dca29012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733368478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
733368478
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1824115495
Short name T114
Test name
Test status
Simulation time 1744606939 ps
CPU time 22.93 seconds
Started Aug 19 05:08:25 PM PDT 24
Finished Aug 19 05:08:49 PM PDT 24
Peak memory 216016 kb
Host smart-6bd8116c-9c1a-4f49-aaea-c7ec0ab10d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824115495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1824115495
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2904542669
Short name T667
Test name
Test status
Simulation time 44739580 ps
CPU time 0.7 seconds
Started Aug 19 06:01:49 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 205576 kb
Host smart-4850a9a9-3877-4d2c-9190-825966677c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904542669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
904542669
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2888626779
Short name T129
Test name
Test status
Simulation time 62316968 ps
CPU time 2.98 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 232880 kb
Host smart-a91a3758-e8fe-4bc7-b07f-39fff989a062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888626779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2888626779
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3481708240
Short name T461
Test name
Test status
Simulation time 28785792 ps
CPU time 0.78 seconds
Started Aug 19 06:01:49 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 206624 kb
Host smart-d733dec4-b3d3-4513-b234-a601a52f0f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481708240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3481708240
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3714765268
Short name T639
Test name
Test status
Simulation time 1568536215 ps
CPU time 22.45 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:02:10 PM PDT 24
Peak memory 217776 kb
Host smart-da40c783-0bad-4a25-8af0-3e91283e3524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714765268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3714765268
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1330330195
Short name T228
Test name
Test status
Simulation time 626867056 ps
CPU time 9.01 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 239884 kb
Host smart-66d2d379-c71e-4c3c-bf22-ff095fdb19af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330330195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1330330195
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3207503772
Short name T812
Test name
Test status
Simulation time 32799252365 ps
CPU time 137.88 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:04:05 PM PDT 24
Peak memory 252728 kb
Host smart-23b841fa-5cf2-4fc5-8a87-1144028b96de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207503772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3207503772
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3112424024
Short name T203
Test name
Test status
Simulation time 1492245635 ps
CPU time 12.66 seconds
Started Aug 19 06:01:50 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 232892 kb
Host smart-f9816fd6-f9a4-4fb1-b11c-da3d2b2a0451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112424024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3112424024
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.42797322
Short name T462
Test name
Test status
Simulation time 12646938504 ps
CPU time 49.05 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 233008 kb
Host smart-c5a676bc-b7e5-4167-9ca7-555433d2a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42797322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.42797322
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.478138345
Short name T906
Test name
Test status
Simulation time 55286102 ps
CPU time 1 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:49 PM PDT 24
Peak memory 216776 kb
Host smart-7a534671-9d55-4ed5-b97c-b2e634040c8a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478138345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.478138345
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.210255531
Short name T781
Test name
Test status
Simulation time 49243930 ps
CPU time 2.33 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:01:50 PM PDT 24
Peak memory 232900 kb
Host smart-041733ca-e000-42b4-a153-6f473d23b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210255531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
210255531
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4115075243
Short name T774
Test name
Test status
Simulation time 22832712208 ps
CPU time 27.42 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 240312 kb
Host smart-d23ec283-fbb6-47fa-9e9d-4d4e4df05f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115075243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4115075243
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1572762468
Short name T907
Test name
Test status
Simulation time 407530776 ps
CPU time 4.93 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:52 PM PDT 24
Peak memory 223260 kb
Host smart-a93d852c-a13e-4f3a-80fa-42907d2bdd81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572762468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1572762468
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2192682485
Short name T477
Test name
Test status
Simulation time 157842303 ps
CPU time 0.95 seconds
Started Aug 19 06:01:46 PM PDT 24
Finished Aug 19 06:01:47 PM PDT 24
Peak memory 207812 kb
Host smart-ef74ffa0-68a4-41fb-9e81-1288f118fdff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192682485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2192682485
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3264660342
Short name T953
Test name
Test status
Simulation time 18527595662 ps
CPU time 26.26 seconds
Started Aug 19 06:01:49 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 219976 kb
Host smart-4065c8da-642d-4ab5-b57d-91bc7a09a48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264660342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3264660342
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.905350895
Short name T1025
Test name
Test status
Simulation time 55090973 ps
CPU time 0.68 seconds
Started Aug 19 06:01:47 PM PDT 24
Finished Aug 19 06:01:48 PM PDT 24
Peak memory 205748 kb
Host smart-e757fe3b-d38d-44b5-83b1-aaaa59c10740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905350895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.905350895
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2046092582
Short name T587
Test name
Test status
Simulation time 357396231 ps
CPU time 5.47 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:02:01 PM PDT 24
Peak memory 216484 kb
Host smart-3bcd79f6-6087-4620-a589-6f726d857cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046092582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2046092582
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1753315072
Short name T9
Test name
Test status
Simulation time 19698756 ps
CPU time 0.72 seconds
Started Aug 19 06:01:45 PM PDT 24
Finished Aug 19 06:01:45 PM PDT 24
Peak memory 206148 kb
Host smart-0a7be996-3481-4940-87ba-7e9637f01c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753315072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1753315072
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1377229852
Short name T891
Test name
Test status
Simulation time 13257571128 ps
CPU time 16.16 seconds
Started Aug 19 06:01:48 PM PDT 24
Finished Aug 19 06:02:04 PM PDT 24
Peak memory 232984 kb
Host smart-32ef185b-82c6-48d1-b884-75f48778db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377229852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1377229852
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1553496612
Short name T566
Test name
Test status
Simulation time 68831862 ps
CPU time 0.69 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:01:55 PM PDT 24
Peak memory 205560 kb
Host smart-213fbcdc-b4b1-4f39-8e37-efc65fcbd766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553496612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
553496612
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2768333920
Short name T490
Test name
Test status
Simulation time 73486095 ps
CPU time 2.13 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 224664 kb
Host smart-07ba50c2-917f-48fe-a6b5-95919b5e5899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768333920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2768333920
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2462492665
Short name T881
Test name
Test status
Simulation time 14697891 ps
CPU time 0.8 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 206468 kb
Host smart-a6a9bce8-a1c7-4a2f-93a7-01c520ffbaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462492665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2462492665
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3907904003
Short name T319
Test name
Test status
Simulation time 3134492212 ps
CPU time 7.01 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:04 PM PDT 24
Peak memory 217904 kb
Host smart-48d6a472-8081-44a9-98c1-a8aba8a190c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907904003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3907904003
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2242683495
Short name T287
Test name
Test status
Simulation time 347227514752 ps
CPU time 652.63 seconds
Started Aug 19 06:01:56 PM PDT 24
Finished Aug 19 06:12:49 PM PDT 24
Peak memory 273992 kb
Host smart-a7837eac-865e-41b5-9764-f6b1f44baf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242683495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2242683495
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2812357961
Short name T863
Test name
Test status
Simulation time 3923684963 ps
CPU time 56.35 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 235968 kb
Host smart-5834bfb9-52e4-45ac-a916-df21e1854318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812357961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2812357961
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3226734228
Short name T740
Test name
Test status
Simulation time 2023746272 ps
CPU time 50.9 seconds
Started Aug 19 06:01:58 PM PDT 24
Finished Aug 19 06:02:49 PM PDT 24
Peak memory 253512 kb
Host smart-4d42600d-808e-4947-a390-5cb4ff2b8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226734228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3226734228
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1062688850
Short name T373
Test name
Test status
Simulation time 634157572 ps
CPU time 3 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 224672 kb
Host smart-d4ebd029-5834-41bb-9082-10e2c079fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062688850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1062688850
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3190962859
Short name T281
Test name
Test status
Simulation time 4401641402 ps
CPU time 22.13 seconds
Started Aug 19 06:01:54 PM PDT 24
Finished Aug 19 06:02:17 PM PDT 24
Peak memory 232956 kb
Host smart-3b4b12e9-a3e3-4f98-813c-1451594c1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190962859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3190962859
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.906133861
Short name T37
Test name
Test status
Simulation time 89756842 ps
CPU time 1.04 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 216776 kb
Host smart-145670da-7acd-4010-8576-2d2657e907c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906133861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.906133861
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2244366913
Short name T608
Test name
Test status
Simulation time 944263273 ps
CPU time 7.14 seconds
Started Aug 19 06:01:54 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 238184 kb
Host smart-a6201134-57bd-46f4-b299-12671f714af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244366913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2244366913
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3754976633
Short name T283
Test name
Test status
Simulation time 838277404 ps
CPU time 5.58 seconds
Started Aug 19 06:01:56 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 238444 kb
Host smart-2c5ba80d-2970-4601-bde2-da271dc559b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754976633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3754976633
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1226465853
Short name T421
Test name
Test status
Simulation time 2902294769 ps
CPU time 13.17 seconds
Started Aug 19 06:01:58 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 219476 kb
Host smart-7461f1ce-a284-4103-933f-c797463955d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1226465853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1226465853
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3000396282
Short name T79
Test name
Test status
Simulation time 70878243 ps
CPU time 0.96 seconds
Started Aug 19 06:01:58 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 235624 kb
Host smart-72ef8bda-d348-4d70-8cbf-b05b273181b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000396282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3000396282
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3648884148
Short name T748
Test name
Test status
Simulation time 170110353 ps
CPU time 0.89 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 206952 kb
Host smart-441ed00b-c356-4492-87ed-b9898d6feed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648884148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3648884148
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3797767546
Short name T668
Test name
Test status
Simulation time 1930337390 ps
CPU time 18.19 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:16 PM PDT 24
Peak memory 216652 kb
Host smart-599d869a-c748-4da5-b413-424fa92b87ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797767546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3797767546
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1367549040
Short name T402
Test name
Test status
Simulation time 1079263829 ps
CPU time 2.99 seconds
Started Aug 19 06:01:56 PM PDT 24
Finished Aug 19 06:01:59 PM PDT 24
Peak memory 216528 kb
Host smart-b26bdd6a-0843-4127-837c-9d14a69f266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367549040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1367549040
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3232051760
Short name T1003
Test name
Test status
Simulation time 54820703 ps
CPU time 1.56 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:01:56 PM PDT 24
Peak memory 216568 kb
Host smart-7a56ca63-268d-4543-847b-e8d5dd3f93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232051760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3232051760
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3248620797
Short name T357
Test name
Test status
Simulation time 200960441 ps
CPU time 1.08 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 207136 kb
Host smart-82eebdec-0197-4440-8574-38363846c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248620797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3248620797
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3777596038
Short name T17
Test name
Test status
Simulation time 15731011821 ps
CPU time 20.35 seconds
Started Aug 19 06:01:55 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 232992 kb
Host smart-adedc6a0-7416-45a9-b980-0f7a053f4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777596038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3777596038
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3527983976
Short name T530
Test name
Test status
Simulation time 40445107 ps
CPU time 0.71 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 205636 kb
Host smart-67d44948-33c9-489c-ae47-6190382dea6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527983976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3527983976
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.212329904
Short name T783
Test name
Test status
Simulation time 10377453233 ps
CPU time 8.35 seconds
Started Aug 19 06:02:34 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 224800 kb
Host smart-43930e60-5012-401b-a703-aa513882ab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212329904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.212329904
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3138801595
Short name T788
Test name
Test status
Simulation time 14778303 ps
CPU time 0.77 seconds
Started Aug 19 06:02:34 PM PDT 24
Finished Aug 19 06:02:35 PM PDT 24
Peak memory 206972 kb
Host smart-70f1314e-3417-4559-baa1-eb37ad082638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138801595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3138801595
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1584739499
Short name T986
Test name
Test status
Simulation time 11487127659 ps
CPU time 36.88 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 257552 kb
Host smart-ade5cc5d-bca6-4d93-be87-3d61d0e36d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584739499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1584739499
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1238624105
Short name T1008
Test name
Test status
Simulation time 39849351129 ps
CPU time 186.15 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 251756 kb
Host smart-e691d969-477c-4d18-9694-8633bfe6570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238624105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1238624105
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4021529977
Short name T495
Test name
Test status
Simulation time 1569225192 ps
CPU time 13.48 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:46 PM PDT 24
Peak memory 232940 kb
Host smart-50227264-2096-46ba-9cb5-a8b9293b9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021529977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4021529977
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3776986074
Short name T413
Test name
Test status
Simulation time 8831111019 ps
CPU time 64.09 seconds
Started Aug 19 06:02:29 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 251740 kb
Host smart-4652d86a-c055-43f7-b9bd-9b9cc41f2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776986074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3776986074
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2759867823
Short name T728
Test name
Test status
Simulation time 268189775 ps
CPU time 4.41 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 224668 kb
Host smart-6ef749dd-7afb-48cb-810e-2d474083a0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759867823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2759867823
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3940697575
Short name T797
Test name
Test status
Simulation time 6090373053 ps
CPU time 45.23 seconds
Started Aug 19 06:02:35 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 232996 kb
Host smart-a53bdd99-4c36-4a76-9188-a6cf4d09dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940697575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3940697575
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3454929772
Short name T36
Test name
Test status
Simulation time 15622073 ps
CPU time 1.04 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:31 PM PDT 24
Peak memory 216772 kb
Host smart-aeb45941-8798-4e74-85a2-37e626f90056
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454929772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3454929772
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1542585006
Short name T271
Test name
Test status
Simulation time 414667488 ps
CPU time 3.52 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 224732 kb
Host smart-bea2236b-ac3f-4554-b03f-b11436cffe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542585006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1542585006
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.106844903
Short name T625
Test name
Test status
Simulation time 508730055 ps
CPU time 5.99 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 232908 kb
Host smart-3b625726-50eb-4b3d-a280-97ed53550703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106844903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.106844903
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.105291586
Short name T815
Test name
Test status
Simulation time 2630243021 ps
CPU time 7 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:39 PM PDT 24
Peak memory 220468 kb
Host smart-5f2e5723-a7bb-44e2-9212-79797101109f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=105291586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.105291586
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1983711084
Short name T936
Test name
Test status
Simulation time 54527582708 ps
CPU time 466.79 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:10:20 PM PDT 24
Peak memory 257648 kb
Host smart-cca4bf14-6e80-4435-aa58-fb07621967f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983711084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1983711084
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4056353794
Short name T324
Test name
Test status
Simulation time 1195332256 ps
CPU time 12 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:42 PM PDT 24
Peak memory 216688 kb
Host smart-035a88bf-d41e-4d30-abe8-7bcfaef49f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056353794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4056353794
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3389563199
Short name T555
Test name
Test status
Simulation time 1301069796 ps
CPU time 2.98 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 208128 kb
Host smart-188774eb-cce7-4a4a-8410-55c9c1a61a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389563199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3389563199
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.785308754
Short name T904
Test name
Test status
Simulation time 85553394 ps
CPU time 1.15 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:33 PM PDT 24
Peak memory 208144 kb
Host smart-4b9b7f54-28cb-446c-a2e7-50139b38c7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785308754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.785308754
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3566994633
Short name T679
Test name
Test status
Simulation time 98505135 ps
CPU time 0.84 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 206144 kb
Host smart-747b69d0-789c-478a-b8ec-bd5fc13bceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566994633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3566994633
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3519937119
Short name T19
Test name
Test status
Simulation time 3597677321 ps
CPU time 10.32 seconds
Started Aug 19 06:02:35 PM PDT 24
Finished Aug 19 06:02:45 PM PDT 24
Peak memory 224764 kb
Host smart-76ab2986-c712-4325-b3ad-662788ddcd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519937119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3519937119
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1673324010
Short name T554
Test name
Test status
Simulation time 36566876 ps
CPU time 0.71 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:39 PM PDT 24
Peak memory 205544 kb
Host smart-a2020745-2f6c-42b1-93cf-e66fcfe71793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673324010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1673324010
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3545609657
Short name T423
Test name
Test status
Simulation time 321107764 ps
CPU time 6.24 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:38 PM PDT 24
Peak memory 232896 kb
Host smart-a1ff09a1-2a74-4db6-af4e-1e8a21ea3125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545609657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3545609657
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1299628052
Short name T712
Test name
Test status
Simulation time 12240116 ps
CPU time 0.73 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 205952 kb
Host smart-78cf54c6-6cda-4392-ae1e-d9fb86ffdc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299628052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1299628052
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3790778820
Short name T336
Test name
Test status
Simulation time 89356149 ps
CPU time 0.77 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 215864 kb
Host smart-856c14cd-76c5-4317-afa4-b840d2e19b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790778820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3790778820
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1054311677
Short name T457
Test name
Test status
Simulation time 80475459631 ps
CPU time 225.67 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:06:26 PM PDT 24
Peak memory 252932 kb
Host smart-e9f0c23f-ff0e-4599-9508-96680cf2c18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054311677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1054311677
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3560818570
Short name T940
Test name
Test status
Simulation time 28659469554 ps
CPU time 298.77 seconds
Started Aug 19 06:02:47 PM PDT 24
Finished Aug 19 06:07:46 PM PDT 24
Peak memory 254412 kb
Host smart-0330a4ac-8536-4b75-b6fb-105f93e6d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560818570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3560818570
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.328755109
Short name T95
Test name
Test status
Simulation time 578436516 ps
CPU time 6.64 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:38 PM PDT 24
Peak memory 224664 kb
Host smart-d731a892-d96b-4b3e-be13-44c703386dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328755109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.328755109
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2451568283
Short name T378
Test name
Test status
Simulation time 487859139 ps
CPU time 2.98 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:36 PM PDT 24
Peak memory 224672 kb
Host smart-21f02dcf-49e7-4c89-84da-fbafc1cd7bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451568283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2451568283
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2248251168
Short name T382
Test name
Test status
Simulation time 446727876 ps
CPU time 3.09 seconds
Started Aug 19 06:02:34 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 224720 kb
Host smart-99e9c634-1b05-4296-9322-c3cccfbe619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248251168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2248251168
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3080627217
Short name T506
Test name
Test status
Simulation time 259865887 ps
CPU time 1.06 seconds
Started Aug 19 06:02:29 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 216740 kb
Host smart-ab691617-3489-4f94-a093-47856d5c52e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080627217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3080627217
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3621047733
Short name T602
Test name
Test status
Simulation time 13518979786 ps
CPU time 17.64 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 224640 kb
Host smart-cfc54605-9af8-4b46-a49f-2b55cc804966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621047733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3621047733
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.443084857
Short name T610
Test name
Test status
Simulation time 478198090 ps
CPU time 3.85 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:35 PM PDT 24
Peak memory 232876 kb
Host smart-9835c38c-2033-4f51-8492-d8afeb839b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443084857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.443084857
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3011165292
Short name T692
Test name
Test status
Simulation time 1053192490 ps
CPU time 10.76 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 222244 kb
Host smart-d59db711-ead4-4512-ab08-16c8ee80cbeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3011165292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3011165292
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4014183840
Short name T1
Test name
Test status
Simulation time 12054289 ps
CPU time 0.69 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:33 PM PDT 24
Peak memory 205740 kb
Host smart-addc03e2-56e7-41af-8519-549f339825eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014183840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4014183840
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3250056523
Short name T481
Test name
Test status
Simulation time 1601370837 ps
CPU time 6.64 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:40 PM PDT 24
Peak memory 216492 kb
Host smart-890360e0-1f9c-444d-b582-f6832a46ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250056523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3250056523
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2094555678
Short name T26
Test name
Test status
Simulation time 25877839 ps
CPU time 1.05 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:33 PM PDT 24
Peak memory 207692 kb
Host smart-be0197b9-cb8b-4577-8936-815457843ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094555678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2094555678
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3832484923
Short name T888
Test name
Test status
Simulation time 57714800 ps
CPU time 0.87 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 207180 kb
Host smart-1a27b7a6-2fb7-46c3-b251-e71c6df9081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832484923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3832484923
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.905176993
Short name T635
Test name
Test status
Simulation time 931982199 ps
CPU time 7.98 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 224604 kb
Host smart-a8c80e95-5d55-45e4-8714-747cb2048642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905176993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.905176993
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3447892262
Short name T968
Test name
Test status
Simulation time 25452789 ps
CPU time 0.73 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 205912 kb
Host smart-78e66040-ed35-4d1a-9aa4-8d7cc80e059c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447892262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3447892262
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4109296875
Short name T626
Test name
Test status
Simulation time 579573335 ps
CPU time 7.04 seconds
Started Aug 19 06:02:44 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 232876 kb
Host smart-82400af9-07e8-4bd8-bd9c-5b81cb0c7970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109296875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4109296875
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.648238003
Short name T612
Test name
Test status
Simulation time 19085896 ps
CPU time 0.81 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:40 PM PDT 24
Peak memory 206636 kb
Host smart-81dd5079-adde-4c01-947b-4dc2ca86027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648238003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.648238003
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.727835284
Short name T189
Test name
Test status
Simulation time 14023374515 ps
CPU time 111.93 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:04:33 PM PDT 24
Peak memory 251256 kb
Host smart-82fb0b05-2d4a-4802-8c73-5a2eaa6f156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727835284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.727835284
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1262508985
Short name T709
Test name
Test status
Simulation time 6008765108 ps
CPU time 34.72 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:03:15 PM PDT 24
Peak memory 249376 kb
Host smart-f9d3c085-d650-4293-bb52-c8d0366c1075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262508985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1262508985
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3386891757
Short name T49
Test name
Test status
Simulation time 243670905081 ps
CPU time 409.09 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 257608 kb
Host smart-8018e56f-26b2-4b67-be47-c7ec8e07bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386891757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3386891757
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1141662515
Short name T765
Test name
Test status
Simulation time 30692067 ps
CPU time 0.79 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 215904 kb
Host smart-bfb15f6e-1a00-4b95-8cb5-a25b4a9ff086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141662515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1141662515
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1137372701
Short name T251
Test name
Test status
Simulation time 149515181 ps
CPU time 2.86 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 224672 kb
Host smart-1dc85d00-2022-4e27-82cf-19d3bef86445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137372701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1137372701
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2480087138
Short name T844
Test name
Test status
Simulation time 3000911003 ps
CPU time 24.82 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:03:05 PM PDT 24
Peak memory 219236 kb
Host smart-20cbaa39-003d-4450-bdaf-de9687a3d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480087138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2480087138
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1333175331
Short name T398
Test name
Test status
Simulation time 121658594 ps
CPU time 1.09 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 216748 kb
Host smart-072721c3-2e52-414b-9e54-7dd2d35a4485
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333175331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1333175331
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3747247676
Short name T229
Test name
Test status
Simulation time 7180186559 ps
CPU time 15.61 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:56 PM PDT 24
Peak memory 232984 kb
Host smart-a3f0ef1b-c405-4143-9a89-ef529e0845a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747247676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3747247676
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.506524496
Short name T743
Test name
Test status
Simulation time 602780069 ps
CPU time 5.96 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 232920 kb
Host smart-145b85aa-1bbd-4de3-bee9-279ada95d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506524496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.506524496
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2590221591
Short name T813
Test name
Test status
Simulation time 1237816631 ps
CPU time 11.45 seconds
Started Aug 19 06:02:38 PM PDT 24
Finished Aug 19 06:02:49 PM PDT 24
Peak memory 223296 kb
Host smart-1177640f-8a8a-4f0b-920c-b5ea155510f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590221591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2590221591
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1727574274
Short name T714
Test name
Test status
Simulation time 32354781299 ps
CPU time 108.36 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 256648 kb
Host smart-842298cd-350a-43a9-8dad-116d12c2a58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727574274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1727574274
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1654318974
Short name T605
Test name
Test status
Simulation time 1067179484 ps
CPU time 2.87 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 216796 kb
Host smart-753f230c-da0f-4bc4-9c65-67ec6f2ddb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654318974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1654318974
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2489743610
Short name T704
Test name
Test status
Simulation time 163011660 ps
CPU time 1 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 207196 kb
Host smart-10c6c3c5-d2da-448a-bf9c-bb3da1ab0707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489743610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2489743610
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.11324729
Short name T942
Test name
Test status
Simulation time 68240898 ps
CPU time 1.04 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 216316 kb
Host smart-d94aa3f4-2be2-470c-a6e4-24aa79926ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11324729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.11324729
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.419611870
Short name T616
Test name
Test status
Simulation time 67229923 ps
CPU time 0.83 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 206148 kb
Host smart-c6fd4f88-192f-453e-9633-66e21116520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419611870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.419611870
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2520998495
Short name T959
Test name
Test status
Simulation time 2575754314 ps
CPU time 3.87 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 224748 kb
Host smart-d978f5c4-00cc-414c-b152-6da0c5f80018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520998495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2520998495
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1661813668
Short name T435
Test name
Test status
Simulation time 49264025 ps
CPU time 0.74 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:40 PM PDT 24
Peak memory 205572 kb
Host smart-01cd8825-1e0b-4fab-b67c-9af9f82603b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661813668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1661813668
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1592201286
Short name T962
Test name
Test status
Simulation time 11567778171 ps
CPU time 11.87 seconds
Started Aug 19 06:02:37 PM PDT 24
Finished Aug 19 06:02:49 PM PDT 24
Peak memory 224968 kb
Host smart-3c29210a-4f58-4529-b387-7e244689ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592201286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1592201286
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1485916817
Short name T580
Test name
Test status
Simulation time 33641873 ps
CPU time 0.78 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 206636 kb
Host smart-e7f54337-01d0-407c-bc87-97bfd9b90c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485916817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1485916817
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.413714138
Short name T600
Test name
Test status
Simulation time 35115714464 ps
CPU time 72.39 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 257560 kb
Host smart-bdfce10d-b053-4f95-af95-1202e50c4ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413714138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.413714138
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1140290611
Short name T877
Test name
Test status
Simulation time 20420907363 ps
CPU time 136.61 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 255588 kb
Host smart-2f07281a-2e68-4da0-827f-8fba0a8a3388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140290611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1140290611
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2901012648
Short name T695
Test name
Test status
Simulation time 699472709 ps
CPU time 9.43 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 224592 kb
Host smart-f361db97-7fe3-48fc-9f79-50cefe736213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901012648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2901012648
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3502475168
Short name T463
Test name
Test status
Simulation time 5054875704 ps
CPU time 72.3 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:03:51 PM PDT 24
Peak memory 251000 kb
Host smart-232354b0-e74f-4eae-b7b4-bba7ccad6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502475168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3502475168
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1981873023
Short name T933
Test name
Test status
Simulation time 333804349 ps
CPU time 3.42 seconds
Started Aug 19 06:02:47 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 224696 kb
Host smart-2f8c260d-aa40-4065-a807-c95c994d7231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981873023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1981873023
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3503742879
Short name T687
Test name
Test status
Simulation time 1164428699 ps
CPU time 5.26 seconds
Started Aug 19 06:02:45 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 224732 kb
Host smart-4e333a4c-95f7-425b-982b-747c70763a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503742879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3503742879
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2676774173
Short name T705
Test name
Test status
Simulation time 448962329 ps
CPU time 1.11 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 216780 kb
Host smart-ebe21b80-811a-48b5-9f0b-991e045fb028
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676774173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2676774173
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.654183418
Short name T887
Test name
Test status
Simulation time 3425568803 ps
CPU time 5.99 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:46 PM PDT 24
Peak memory 224740 kb
Host smart-51965927-e858-4f29-8b96-24fc9be0f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654183418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.654183418
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3801018423
Short name T539
Test name
Test status
Simulation time 3050469787 ps
CPU time 9.72 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 224792 kb
Host smart-62f90c17-06f2-43db-9741-463d62437432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801018423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3801018423
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1429714480
Short name T393
Test name
Test status
Simulation time 431814399 ps
CPU time 4.03 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 222772 kb
Host smart-74503f40-e391-49ea-965d-1f68f969a6a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1429714480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1429714480
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4135878611
Short name T321
Test name
Test status
Simulation time 5132263656 ps
CPU time 24.89 seconds
Started Aug 19 06:02:44 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 216648 kb
Host smart-672600bd-4ab0-472b-90c6-132be16b024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135878611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4135878611
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2050894616
Short name T854
Test name
Test status
Simulation time 623766986 ps
CPU time 4.26 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:02:47 PM PDT 24
Peak memory 216512 kb
Host smart-83efd9f3-905b-4e20-9f24-e3618085167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050894616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2050894616
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.223376154
Short name T429
Test name
Test status
Simulation time 357634328 ps
CPU time 1.26 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 208272 kb
Host smart-f49b8d3e-0524-4672-bc3d-5ad1e36c5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223376154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.223376154
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2375837254
Short name T584
Test name
Test status
Simulation time 76096858 ps
CPU time 0.75 seconds
Started Aug 19 06:02:45 PM PDT 24
Finished Aug 19 06:02:46 PM PDT 24
Peak memory 206152 kb
Host smart-dffccc31-4608-4d04-96b2-74467dd374c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375837254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2375837254
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.924292678
Short name T256
Test name
Test status
Simulation time 6510726157 ps
CPU time 9.25 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:48 PM PDT 24
Peak memory 235448 kb
Host smart-9f193a8e-f1d2-4e93-a627-26c62c389b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924292678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.924292678
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.901643771
Short name T636
Test name
Test status
Simulation time 17367270 ps
CPU time 0.69 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 205900 kb
Host smart-2bce5bb1-aaf6-4c7c-8685-3f36bc53f80f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901643771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.901643771
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2845665999
Short name T537
Test name
Test status
Simulation time 579227876 ps
CPU time 4.05 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 232864 kb
Host smart-9ddda2f0-0065-439e-82f2-3e4e6302f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845665999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2845665999
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2178186308
Short name T550
Test name
Test status
Simulation time 37157306 ps
CPU time 0.77 seconds
Started Aug 19 06:02:47 PM PDT 24
Finished Aug 19 06:02:48 PM PDT 24
Peak memory 206612 kb
Host smart-5ec54c65-f9b4-4e44-a5ce-743bb5057e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178186308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2178186308
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3524536553
Short name T531
Test name
Test status
Simulation time 6697043642 ps
CPU time 68.35 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 249400 kb
Host smart-fa77f01b-e3cf-4b44-b592-379acab74a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524536553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3524536553
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3589713932
Short name T556
Test name
Test status
Simulation time 4619566900 ps
CPU time 42.85 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:03:31 PM PDT 24
Peak memory 253664 kb
Host smart-7939d633-1d55-43ee-90b6-e02cf35b398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589713932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3589713932
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3529606671
Short name T326
Test name
Test status
Simulation time 30226501449 ps
CPU time 40.87 seconds
Started Aug 19 06:02:47 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 219812 kb
Host smart-dcb2c963-6702-457c-8fd1-fe71d0190174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529606671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3529606671
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3198536571
Short name T579
Test name
Test status
Simulation time 1342846441 ps
CPU time 6.42 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:47 PM PDT 24
Peak memory 224732 kb
Host smart-dddc25dc-aa6d-4e81-b0cf-f53ece1a9b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198536571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3198536571
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3674293030
Short name T96
Test name
Test status
Simulation time 12326565476 ps
CPU time 91.12 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 262988 kb
Host smart-5e97ddac-1002-498a-b506-4a0edb662094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674293030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3674293030
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.953620333
Short name T101
Test name
Test status
Simulation time 24237386139 ps
CPU time 12.72 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:54 PM PDT 24
Peak memory 232972 kb
Host smart-d672082c-cb8b-48cf-8c9b-f198d47131f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953620333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.953620333
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3419274689
Short name T210
Test name
Test status
Simulation time 10542517266 ps
CPU time 40.25 seconds
Started Aug 19 06:02:45 PM PDT 24
Finished Aug 19 06:03:26 PM PDT 24
Peak memory 240812 kb
Host smart-d9181957-dde9-44f8-8f3f-0974e7771d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419274689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3419274689
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3126041115
Short name T864
Test name
Test status
Simulation time 30759383 ps
CPU time 1.04 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:42 PM PDT 24
Peak memory 218060 kb
Host smart-b6cfdc2b-68f6-4735-bdad-03edfe4cf77c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126041115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3126041115
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2697839369
Short name T870
Test name
Test status
Simulation time 2786404219 ps
CPU time 9.71 seconds
Started Aug 19 06:02:38 PM PDT 24
Finished Aug 19 06:02:47 PM PDT 24
Peak memory 224804 kb
Host smart-db6d7ccb-126f-431f-8eec-2ee1347e645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697839369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2697839369
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.536096329
Short name T431
Test name
Test status
Simulation time 31466610533 ps
CPU time 10.99 seconds
Started Aug 19 06:02:43 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 232948 kb
Host smart-5cc32215-e830-48cf-9197-6db0d02f758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536096329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.536096329
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.156021389
Short name T160
Test name
Test status
Simulation time 591191834 ps
CPU time 3.67 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:02:56 PM PDT 24
Peak memory 222448 kb
Host smart-49b3aa7a-f5a0-4b4e-bf11-6dc171b46ec2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=156021389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.156021389
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3527363277
Short name T627
Test name
Test status
Simulation time 201543668 ps
CPU time 0.95 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 205688 kb
Host smart-c70e478f-826c-4dde-a66c-ff39770c8fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527363277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3527363277
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.860052375
Short name T934
Test name
Test status
Simulation time 229743790 ps
CPU time 3.27 seconds
Started Aug 19 06:02:41 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 216632 kb
Host smart-f87c98e3-d2cc-4786-bfa5-0b6a0725d671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860052375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.860052375
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1424431261
Short name T466
Test name
Test status
Simulation time 4610523009 ps
CPU time 4.83 seconds
Started Aug 19 06:02:39 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 216552 kb
Host smart-95a3a747-c04e-438c-a4fb-8580b3291a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424431261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1424431261
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.734460227
Short name T547
Test name
Test status
Simulation time 95982874 ps
CPU time 4.24 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:44 PM PDT 24
Peak memory 216548 kb
Host smart-984c2a56-add8-40ba-a1be-fac5a0cbd73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734460227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.734460227
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2154868889
Short name T54
Test name
Test status
Simulation time 82397603 ps
CPU time 0.77 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:02:41 PM PDT 24
Peak memory 206132 kb
Host smart-f9e65366-20d1-4dba-8646-680e94a8c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154868889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2154868889
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2610907441
Short name T603
Test name
Test status
Simulation time 82680673 ps
CPU time 2.83 seconds
Started Aug 19 06:02:42 PM PDT 24
Finished Aug 19 06:02:45 PM PDT 24
Peak memory 232884 kb
Host smart-89c6ea9f-3c8f-4e54-ac22-42b4a2a2976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610907441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2610907441
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2052870896
Short name T649
Test name
Test status
Simulation time 448080462 ps
CPU time 3.74 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:02:56 PM PDT 24
Peak memory 232808 kb
Host smart-680df417-ca1e-43d5-906d-f39daeadaf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052870896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2052870896
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.458352646
Short name T69
Test name
Test status
Simulation time 13067494 ps
CPU time 0.74 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 205568 kb
Host smart-6a1e75ae-bb83-4900-83fd-10d66620e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458352646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.458352646
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2556156641
Short name T703
Test name
Test status
Simulation time 7064264577 ps
CPU time 24.04 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:03:15 PM PDT 24
Peak memory 235728 kb
Host smart-0875c922-173b-4487-8379-29f0c2d17a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556156641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2556156641
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3824556
Short name T913
Test name
Test status
Simulation time 58817857917 ps
CPU time 120.9 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:04:51 PM PDT 24
Peak memory 239456 kb
Host smart-77a1165f-3bde-4adf-b6f9-4a2d0e7b72bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3824556
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1755365865
Short name T597
Test name
Test status
Simulation time 18020829314 ps
CPU time 151.19 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:05:20 PM PDT 24
Peak memory 249200 kb
Host smart-04bfe52b-f052-4d71-b60e-18409e1bddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755365865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1755365865
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2221378989
Short name T952
Test name
Test status
Simulation time 6579020108 ps
CPU time 48.93 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:03:40 PM PDT 24
Peak memory 249436 kb
Host smart-77dcdcca-3e58-4697-9f78-40d00d7b7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221378989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2221378989
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2446085336
Short name T468
Test name
Test status
Simulation time 1993383196 ps
CPU time 10.62 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 224680 kb
Host smart-8552553a-3542-4b4f-a631-3221d863fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446085336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2446085336
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2567851639
Short name T249
Test name
Test status
Simulation time 429001197 ps
CPU time 6.87 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 224600 kb
Host smart-b64c04ba-3b1c-4217-885c-d1dfed88c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567851639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2567851639
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3069323083
Short name T509
Test name
Test status
Simulation time 37383422365 ps
CPU time 81.14 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 224764 kb
Host smart-f1ab0e6c-4ac9-4e47-88a2-03a93a3d69bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069323083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3069323083
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2357896219
Short name T731
Test name
Test status
Simulation time 51437630 ps
CPU time 0.99 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 218052 kb
Host smart-a806fd8e-cff5-4591-9ff3-f5d8b9f616b4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357896219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2357896219
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.210980412
Short name T267
Test name
Test status
Simulation time 398766660 ps
CPU time 2.4 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:02:54 PM PDT 24
Peak memory 224692 kb
Host smart-0b5416bb-bdb4-4131-b0bc-d754655c0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210980412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.210980412
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1307371008
Short name T702
Test name
Test status
Simulation time 1577433043 ps
CPU time 8.83 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:03:01 PM PDT 24
Peak memory 240248 kb
Host smart-894193fe-fbd7-44a4-9753-54ef295b0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307371008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1307371008
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1411713268
Short name T162
Test name
Test status
Simulation time 1744109866 ps
CPU time 5.13 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:02:54 PM PDT 24
Peak memory 221224 kb
Host smart-1a0d7a10-4bd0-4a96-abe0-fe19787b92ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411713268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1411713268
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3398293433
Short name T761
Test name
Test status
Simulation time 254832245 ps
CPU time 1.11 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 207776 kb
Host smart-34078eb3-3c83-4095-88e4-e1a4333e94a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398293433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3398293433
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2581823206
Short name T441
Test name
Test status
Simulation time 23603697394 ps
CPU time 18.58 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:03:06 PM PDT 24
Peak memory 216556 kb
Host smart-c6c01439-cc7b-4094-9500-f87fdf1977d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581823206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2581823206
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.387590938
Short name T420
Test name
Test status
Simulation time 5178982348 ps
CPU time 5.21 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:02:56 PM PDT 24
Peak memory 216608 kb
Host smart-28a8c2d8-20a9-4d19-af89-1b084b00cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387590938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.387590938
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3877928966
Short name T869
Test name
Test status
Simulation time 27864370 ps
CPU time 0.82 seconds
Started Aug 19 06:03:02 PM PDT 24
Finished Aug 19 06:03:03 PM PDT 24
Peak memory 206140 kb
Host smart-8a11adb2-bf1f-446f-be59-4cc62475eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877928966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3877928966
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2648254471
Short name T347
Test name
Test status
Simulation time 64369414 ps
CPU time 0.77 seconds
Started Aug 19 06:02:53 PM PDT 24
Finished Aug 19 06:02:54 PM PDT 24
Peak memory 206132 kb
Host smart-f284aeb3-363a-4073-bcd0-7276ede3bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648254471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2648254471
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.565560104
Short name T504
Test name
Test status
Simulation time 111211685 ps
CPU time 2.04 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:02:50 PM PDT 24
Peak memory 224296 kb
Host smart-cc1ab3bd-af91-4afc-8f36-84eeaeea0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565560104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.565560104
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.613151122
Short name T76
Test name
Test status
Simulation time 18120695 ps
CPU time 0.72 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 204996 kb
Host smart-4bce91a1-10dc-428c-a667-bc1045bec97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613151122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.613151122
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4147705924
Short name T560
Test name
Test status
Simulation time 3178346338 ps
CPU time 24.17 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:03:14 PM PDT 24
Peak memory 233012 kb
Host smart-cce756cd-c5b1-4a6c-a8ad-e13395c8492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147705924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4147705924
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2200161923
Short name T62
Test name
Test status
Simulation time 18245792 ps
CPU time 0.81 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 206336 kb
Host smart-81c32fbf-1aac-4946-acb7-4e738a23153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200161923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2200161923
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1489696474
Short name T301
Test name
Test status
Simulation time 147769328371 ps
CPU time 80.18 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 238840 kb
Host smart-0c36d339-0662-425a-85d5-6f180b9d82d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489696474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1489696474
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4062951211
Short name T937
Test name
Test status
Simulation time 335708019563 ps
CPU time 347.82 seconds
Started Aug 19 06:02:53 PM PDT 24
Finished Aug 19 06:08:41 PM PDT 24
Peak memory 256020 kb
Host smart-bcae3ab7-79da-4b2c-b76b-a3cadacbea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062951211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4062951211
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2093756895
Short name T739
Test name
Test status
Simulation time 864286048 ps
CPU time 15.96 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:03:06 PM PDT 24
Peak memory 232980 kb
Host smart-9c18c40c-3706-4d9c-80ca-4b7164b69b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093756895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2093756895
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1571888000
Short name T161
Test name
Test status
Simulation time 109351459 ps
CPU time 6.9 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:02:57 PM PDT 24
Peak memory 241088 kb
Host smart-62ed4a8c-1436-4b52-9f6f-c233cf7ac2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571888000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1571888000
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2638269296
Short name T643
Test name
Test status
Simulation time 23897457888 ps
CPU time 72.69 seconds
Started Aug 19 06:02:54 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 249400 kb
Host smart-1336f211-1186-4c0f-a14b-48febad78894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638269296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2638269296
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3110708771
Short name T434
Test name
Test status
Simulation time 92975268 ps
CPU time 2.22 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 224740 kb
Host smart-b6db4553-48ae-4306-bdcb-9d1ee2375760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110708771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3110708771
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4156190711
Short name T763
Test name
Test status
Simulation time 42396356983 ps
CPU time 63.53 seconds
Started Aug 19 06:02:54 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 232936 kb
Host smart-cc6dd1fa-1315-487a-81ce-0e0c4a5f6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156190711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4156190711
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.734856376
Short name T433
Test name
Test status
Simulation time 92525708 ps
CPU time 1.06 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 216776 kb
Host smart-263de8aa-7c05-465b-81d1-addd9028422d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734856376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.734856376
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3152554203
Short name T419
Test name
Test status
Simulation time 2319612292 ps
CPU time 7.58 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 232964 kb
Host smart-49fc77c3-5df7-46f1-bc12-3faf0d05d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152554203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3152554203
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2981515744
Short name T12
Test name
Test status
Simulation time 728523673 ps
CPU time 3.88 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 224728 kb
Host smart-bda0f7f2-f33a-4e43-a2e4-99a586e322c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981515744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2981515744
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.173000754
Short name T884
Test name
Test status
Simulation time 1376085379 ps
CPU time 12.19 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 219480 kb
Host smart-b2bbfd80-d118-4499-b17a-f626f746fe09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=173000754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.173000754
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.371757280
Short name T817
Test name
Test status
Simulation time 7015372991 ps
CPU time 34.94 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:03:25 PM PDT 24
Peak memory 216512 kb
Host smart-4393cb29-3103-4b9f-92d1-87961a1a881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371757280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.371757280
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1995156031
Short name T619
Test name
Test status
Simulation time 761846692 ps
CPU time 1.84 seconds
Started Aug 19 06:02:53 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 216416 kb
Host smart-92be69d6-bbdf-4203-9722-7f4627a9d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995156031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1995156031
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3093041066
Short name T446
Test name
Test status
Simulation time 38066656 ps
CPU time 0.86 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 206184 kb
Host smart-f88dc065-2a74-4565-90a3-09fc9ae0daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093041066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3093041066
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1088625816
Short name T710
Test name
Test status
Simulation time 967389083 ps
CPU time 13.99 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:03:02 PM PDT 24
Peak memory 240264 kb
Host smart-65443275-8fde-4722-81a6-9b7b5386df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088625816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1088625816
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4194456818
Short name T820
Test name
Test status
Simulation time 33286574 ps
CPU time 0.73 seconds
Started Aug 19 06:02:59 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 204948 kb
Host smart-ef779fa0-9748-4479-be17-af0e2b575b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194456818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4194456818
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2199208904
Short name T261
Test name
Test status
Simulation time 165166647 ps
CPU time 3.17 seconds
Started Aug 19 06:02:59 PM PDT 24
Finished Aug 19 06:03:02 PM PDT 24
Peak memory 224676 kb
Host smart-9fc6aeaa-7d0e-4d9f-b96a-ea74ed197e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199208904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2199208904
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.181363295
Short name T417
Test name
Test status
Simulation time 64435130 ps
CPU time 0.79 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:02:53 PM PDT 24
Peak memory 206636 kb
Host smart-b088e82b-7db9-4f87-aa3e-1516cbd33184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181363295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.181363295
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.841467658
Short name T595
Test name
Test status
Simulation time 19113690485 ps
CPU time 148.3 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:05:17 PM PDT 24
Peak memory 252080 kb
Host smart-bb7e053c-a1af-4c72-b2b5-59694f258833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841467658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.841467658
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.75798277
Short name T837
Test name
Test status
Simulation time 29678511508 ps
CPU time 46.27 seconds
Started Aug 19 06:02:48 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 224844 kb
Host smart-84955d4f-19e2-4635-a1bc-d072cf2c8fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75798277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.75798277
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.555123217
Short name T803
Test name
Test status
Simulation time 21421356507 ps
CPU time 36.42 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 237360 kb
Host smart-7845deeb-30ae-4be3-96fa-79baa1e4dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555123217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.555123217
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1682647379
Short name T599
Test name
Test status
Simulation time 543222788 ps
CPU time 3.57 seconds
Started Aug 19 06:02:49 PM PDT 24
Finished Aug 19 06:02:53 PM PDT 24
Peak memory 224700 kb
Host smart-fbc48834-5ff5-4f9a-8dd0-24d79b7cbd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682647379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1682647379
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1634661478
Short name T209
Test name
Test status
Simulation time 45604168855 ps
CPU time 90.5 seconds
Started Aug 19 06:02:53 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 241036 kb
Host smart-d5deaccb-9839-40aa-8248-0125d64ed0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634661478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1634661478
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2160846104
Short name T254
Test name
Test status
Simulation time 98237064 ps
CPU time 2.33 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 224736 kb
Host smart-91c44f2c-63f4-476e-b8ea-5611f5630c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160846104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2160846104
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3436238276
Short name T400
Test name
Test status
Simulation time 288191299 ps
CPU time 4.82 seconds
Started Aug 19 06:02:54 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 220076 kb
Host smart-ad868dc9-1d9f-44bd-b5c7-54b05b3357f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436238276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3436238276
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4093409472
Short name T634
Test name
Test status
Simulation time 399016645 ps
CPU time 1.1 seconds
Started Aug 19 06:02:50 PM PDT 24
Finished Aug 19 06:02:51 PM PDT 24
Peak memory 216772 kb
Host smart-f039de16-c357-4ad4-99e7-ee415638c6d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093409472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4093409472
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.907871702
Short name T661
Test name
Test status
Simulation time 304004132 ps
CPU time 2.43 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 223888 kb
Host smart-8c7e54b0-aede-4ca9-acad-13464a4d3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907871702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.907871702
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1606495083
Short name T947
Test name
Test status
Simulation time 5216136790 ps
CPU time 15.62 seconds
Started Aug 19 06:02:52 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 233004 kb
Host smart-8795cd71-b998-498c-a1f4-4679367c0767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606495083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1606495083
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4121390867
Short name T1017
Test name
Test status
Simulation time 2310661320 ps
CPU time 12.66 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 219580 kb
Host smart-49b0215d-a2c5-4044-9300-7ee206716b3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4121390867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4121390867
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3139294321
Short name T174
Test name
Test status
Simulation time 2245423093 ps
CPU time 37.44 seconds
Started Aug 19 06:02:56 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 249548 kb
Host smart-4040b1e9-4f2b-4888-8f25-86d9ec38752a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139294321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3139294321
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1161990207
Short name T317
Test name
Test status
Simulation time 2335603004 ps
CPU time 21.9 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 220504 kb
Host smart-760365d6-12ca-4924-b2a3-46b25e96314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161990207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1161990207
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2988151562
Short name T474
Test name
Test status
Simulation time 41124622 ps
CPU time 0.74 seconds
Started Aug 19 06:02:51 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 205456 kb
Host smart-b438e5e4-c758-4231-abc4-17ee6f6e0262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988151562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2988151562
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3092244533
Short name T5
Test name
Test status
Simulation time 21276350 ps
CPU time 0.8 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 206136 kb
Host smart-e16cac8e-709f-40a6-b549-aec294def176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092244533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3092244533
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2807405459
Short name T985
Test name
Test status
Simulation time 179581616 ps
CPU time 0.86 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:02:59 PM PDT 24
Peak memory 206132 kb
Host smart-f315ef04-9cb2-45d2-993e-292b7e5caefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807405459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2807405459
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2306935959
Short name T1005
Test name
Test status
Simulation time 5840013726 ps
CPU time 6.72 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:05 PM PDT 24
Peak memory 232928 kb
Host smart-4f075d98-26c5-4bc8-a819-be6006edd5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306935959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2306935959
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.407757110
Short name T538
Test name
Test status
Simulation time 14446348 ps
CPU time 0.72 seconds
Started Aug 19 06:03:01 PM PDT 24
Finished Aug 19 06:03:01 PM PDT 24
Peak memory 205544 kb
Host smart-02358e5b-d557-457d-bc7f-fbd50660359b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407757110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.407757110
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.731119110
Short name T798
Test name
Test status
Simulation time 907540461 ps
CPU time 9.29 seconds
Started Aug 19 06:03:02 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 224700 kb
Host smart-e032cd0a-68c0-4185-89b2-27c8e16e5c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731119110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.731119110
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.635531138
Short name T215
Test name
Test status
Simulation time 39828704641 ps
CPU time 201.6 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:06:20 PM PDT 24
Peak memory 265728 kb
Host smart-d75a644d-4405-489e-8606-e377280f997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635531138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.635531138
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1087674110
Short name T226
Test name
Test status
Simulation time 24917208390 ps
CPU time 161.24 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 253320 kb
Host smart-ad469f34-f201-43a3-be78-c93572aeb6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087674110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1087674110
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3180069543
Short name T935
Test name
Test status
Simulation time 5867960784 ps
CPU time 8.22 seconds
Started Aug 19 06:03:02 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 224756 kb
Host smart-a5a9268d-8928-451b-ac37-df48894cb755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180069543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3180069543
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1010687628
Short name T275
Test name
Test status
Simulation time 4094492221 ps
CPU time 11.36 seconds
Started Aug 19 06:02:56 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 232996 kb
Host smart-e1dc5278-13d9-47c3-b3b1-3c9284a57042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010687628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1010687628
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.103503860
Short name T660
Test name
Test status
Simulation time 335542687 ps
CPU time 3.23 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 224656 kb
Host smart-3084a9b4-49d9-45c3-af78-fc4e1f12db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103503860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.103503860
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2203611136
Short name T617
Test name
Test status
Simulation time 2229213851 ps
CPU time 26.63 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:03:24 PM PDT 24
Peak memory 234000 kb
Host smart-c8694721-6c94-4afd-9961-c0f4d85d7c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203611136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2203611136
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.968093682
Short name T957
Test name
Test status
Simulation time 31791148 ps
CPU time 0.99 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 217992 kb
Host smart-f303acb7-928b-4162-a03d-84ea980b7098
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968093682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.968093682
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2491619386
Short name T677
Test name
Test status
Simulation time 3005733599 ps
CPU time 7.33 seconds
Started Aug 19 06:02:56 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 233012 kb
Host smart-6f9a311d-3571-454d-8f91-02a9f6180415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491619386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2491619386
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1355026023
Short name T845
Test name
Test status
Simulation time 4147343261 ps
CPU time 11.74 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 248812 kb
Host smart-f40cf29c-79f2-4c9b-8f38-d0e00c01391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355026023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1355026023
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1811033107
Short name T516
Test name
Test status
Simulation time 4840324106 ps
CPU time 9.86 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 220456 kb
Host smart-2a06c0ca-e317-4ed9-8cc3-b14b181819cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811033107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1811033107
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3875489425
Short name T737
Test name
Test status
Simulation time 31251952841 ps
CPU time 114.55 seconds
Started Aug 19 06:03:00 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 250324 kb
Host smart-9d93b3a1-493d-41ab-b800-e797b5313a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875489425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3875489425
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4073184919
Short name T25
Test name
Test status
Simulation time 2620456233 ps
CPU time 4.08 seconds
Started Aug 19 06:03:03 PM PDT 24
Finished Aug 19 06:03:07 PM PDT 24
Peak memory 216604 kb
Host smart-c77d88c6-c3cf-465e-b06a-ea298e63dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073184919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4073184919
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1754550952
Short name T399
Test name
Test status
Simulation time 20393524 ps
CPU time 0.71 seconds
Started Aug 19 06:03:00 PM PDT 24
Finished Aug 19 06:03:01 PM PDT 24
Peak memory 205744 kb
Host smart-c64ba4e5-c341-401a-bfc2-b99c2306ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754550952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1754550952
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.606220384
Short name T776
Test name
Test status
Simulation time 25614677 ps
CPU time 1 seconds
Started Aug 19 06:03:01 PM PDT 24
Finished Aug 19 06:03:02 PM PDT 24
Peak memory 207668 kb
Host smart-4335ec65-08b0-4d43-8562-6c9a1c194ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606220384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.606220384
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2302527179
Short name T486
Test name
Test status
Simulation time 40376322 ps
CPU time 0.82 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 206152 kb
Host smart-4bfe6ad3-9add-4d28-802c-1527879c73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302527179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2302527179
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1091760330
Short name T866
Test name
Test status
Simulation time 3159536751 ps
CPU time 2.71 seconds
Started Aug 19 06:03:03 PM PDT 24
Finished Aug 19 06:03:06 PM PDT 24
Peak memory 224720 kb
Host smart-4329fb0b-8f20-4e90-b377-adafbfefe721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091760330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1091760330
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1245400713
Short name T789
Test name
Test status
Simulation time 18144098 ps
CPU time 0.72 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 205524 kb
Host smart-170c7da5-c4d0-4d3c-97ae-6b44f7407871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245400713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1245400713
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4144892070
Short name T436
Test name
Test status
Simulation time 3712712590 ps
CPU time 10.22 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:17 PM PDT 24
Peak memory 232916 kb
Host smart-11a8d580-ac0c-4565-80c8-5e9aa945f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144892070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4144892070
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.553710107
Short name T929
Test name
Test status
Simulation time 27527826 ps
CPU time 0.82 seconds
Started Aug 19 06:02:59 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 206636 kb
Host smart-d9fc1fc1-4b23-4f18-9548-5681812a653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553710107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.553710107
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2314854653
Short name T696
Test name
Test status
Simulation time 2596480366 ps
CPU time 31.48 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:40 PM PDT 24
Peak memory 252788 kb
Host smart-552a6378-7769-467f-9ab4-8667fcb10dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314854653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2314854653
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3903501925
Short name T325
Test name
Test status
Simulation time 5669108502 ps
CPU time 34.27 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:42 PM PDT 24
Peak memory 224840 kb
Host smart-729c2b71-b83d-47ba-9043-3937ca84aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903501925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3903501925
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.846060746
Short name T238
Test name
Test status
Simulation time 25599569588 ps
CPU time 123.32 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:05:12 PM PDT 24
Peak memory 249964 kb
Host smart-8d04a6f8-7db5-4bf9-a71b-579d1ce6a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846060746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.846060746
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3200454403
Short name T954
Test name
Test status
Simulation time 260023572 ps
CPU time 6.64 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:14 PM PDT 24
Peak memory 232964 kb
Host smart-aea94d25-c361-4cef-9268-ed2af322208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200454403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3200454403
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3519814337
Short name T214
Test name
Test status
Simulation time 24836931690 ps
CPU time 99.86 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 251824 kb
Host smart-345a9c1b-6727-4de9-8aa6-8d3b0ccf7364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519814337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3519814337
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.685527755
Short name T833
Test name
Test status
Simulation time 6963788897 ps
CPU time 10.7 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 224736 kb
Host smart-27b68f7f-1f81-43cc-8353-3ef821cae793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685527755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.685527755
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.585640620
Short name T725
Test name
Test status
Simulation time 1560551084 ps
CPU time 22.49 seconds
Started Aug 19 06:02:56 PM PDT 24
Finished Aug 19 06:03:19 PM PDT 24
Peak memory 232880 kb
Host smart-54de6c13-c00b-43c3-b384-718dc2e803f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585640620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.585640620
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.37754708
Short name T277
Test name
Test status
Simulation time 14978326123 ps
CPU time 11.77 seconds
Started Aug 19 06:03:02 PM PDT 24
Finished Aug 19 06:03:14 PM PDT 24
Peak memory 224732 kb
Host smart-edbddbbb-3614-4f03-81a3-083cc2966443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37754708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.37754708
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1383400264
Short name T362
Test name
Test status
Simulation time 439681155 ps
CPU time 2.16 seconds
Started Aug 19 06:02:55 PM PDT 24
Finished Aug 19 06:02:57 PM PDT 24
Peak memory 223192 kb
Host smart-18a90a66-0d67-4966-b4e5-86b347156f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383400264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1383400264
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.950114448
Short name T415
Test name
Test status
Simulation time 128646992 ps
CPU time 4.13 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 223148 kb
Host smart-0d6a1dd6-23bf-47fa-9710-1159b5e79951
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=950114448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.950114448
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3017509143
Short name T825
Test name
Test status
Simulation time 21856311371 ps
CPU time 26.57 seconds
Started Aug 19 06:02:58 PM PDT 24
Finished Aug 19 06:03:25 PM PDT 24
Peak memory 216564 kb
Host smart-df1f7649-f281-48a6-a42a-3d7dff79323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017509143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3017509143
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3410359648
Short name T585
Test name
Test status
Simulation time 51791805 ps
CPU time 0.71 seconds
Started Aug 19 06:02:59 PM PDT 24
Finished Aug 19 06:03:00 PM PDT 24
Peak memory 205764 kb
Host smart-8790a1a7-53f1-4240-9ace-e33272847b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410359648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3410359648
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1352866582
Short name T520
Test name
Test status
Simulation time 77169734 ps
CPU time 1.81 seconds
Started Aug 19 06:02:56 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 216488 kb
Host smart-cca3602b-1a37-462c-bed5-3bb70f640923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352866582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1352866582
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1416462924
Short name T471
Test name
Test status
Simulation time 81334911 ps
CPU time 0.94 seconds
Started Aug 19 06:02:57 PM PDT 24
Finished Aug 19 06:02:58 PM PDT 24
Peak memory 206148 kb
Host smart-35c2439f-5f42-4d81-a154-5581f09c42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416462924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1416462924
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3851776442
Short name T223
Test name
Test status
Simulation time 5971020178 ps
CPU time 10.48 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 224768 kb
Host smart-e3c87d53-0937-4bd2-9225-59370cb52adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851776442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3851776442
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3940000587
Short name T377
Test name
Test status
Simulation time 23145903 ps
CPU time 0.73 seconds
Started Aug 19 06:02:01 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 204972 kb
Host smart-901913f2-0b82-4ad1-948a-6777b9245294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940000587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
940000587
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2366206197
Short name T410
Test name
Test status
Simulation time 82409418 ps
CPU time 2.15 seconds
Started Aug 19 06:02:01 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 224276 kb
Host smart-565626e2-2396-43f4-a90a-7209029279f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366206197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2366206197
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3715754
Short name T337
Test name
Test status
Simulation time 17274547 ps
CPU time 0.8 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 205428 kb
Host smart-d9ce0795-6163-4ecc-ba59-647211fb7d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3715754
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1451510035
Short name T989
Test name
Test status
Simulation time 3245404969 ps
CPU time 11.06 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 234196 kb
Host smart-19b96c12-3fdb-4892-9f7f-ab5bf2ce510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451510035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1451510035
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2795744750
Short name T291
Test name
Test status
Simulation time 2989464227 ps
CPU time 32.42 seconds
Started Aug 19 06:02:00 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 234792 kb
Host smart-a6f65719-7adb-4312-a13a-4003c7c8125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795744750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2795744750
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1207751617
Short name T154
Test name
Test status
Simulation time 9720466820 ps
CPU time 124.09 seconds
Started Aug 19 06:02:01 PM PDT 24
Finished Aug 19 06:04:06 PM PDT 24
Peak memory 253328 kb
Host smart-82c459b3-b958-4b8c-aafc-516998ce5f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207751617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1207751617
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2068159998
Short name T480
Test name
Test status
Simulation time 488927065 ps
CPU time 5.89 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 224676 kb
Host smart-1b4710b7-56f3-4f3e-9edd-8727102d50bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068159998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2068159998
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3882164686
Short name T523
Test name
Test status
Simulation time 284895346448 ps
CPU time 103.76 seconds
Started Aug 19 06:02:00 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 224792 kb
Host smart-49e66353-a088-4289-862c-3f597992c013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882164686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3882164686
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.670379229
Short name T526
Test name
Test status
Simulation time 451198314 ps
CPU time 6.6 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:03 PM PDT 24
Peak memory 232908 kb
Host smart-6543ee9b-1bc3-4fbf-868b-e911207d72e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670379229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.670379229
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1609890777
Short name T919
Test name
Test status
Simulation time 242019070 ps
CPU time 7.42 seconds
Started Aug 19 06:02:02 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 232952 kb
Host smart-15ef8d91-92c1-446f-ae68-40542bff78d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609890777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1609890777
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3135519696
Short name T65
Test name
Test status
Simulation time 146533791 ps
CPU time 1.02 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:00 PM PDT 24
Peak memory 216764 kb
Host smart-44042fa5-aefc-4ef4-9cbd-5160c88619c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135519696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3135519696
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.263734971
Short name T949
Test name
Test status
Simulation time 17762896386 ps
CPU time 13.93 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:13 PM PDT 24
Peak memory 224712 kb
Host smart-462f091f-29ee-4177-80d1-d75b8b554b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263734971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
263734971
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.879060416
Short name T895
Test name
Test status
Simulation time 610490900 ps
CPU time 3.22 seconds
Started Aug 19 06:02:02 PM PDT 24
Finished Aug 19 06:02:05 PM PDT 24
Peak memory 224688 kb
Host smart-f4849414-1a6c-4ccb-991f-0d3ab1fa67d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879060416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.879060416
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1325843704
Short name T831
Test name
Test status
Simulation time 197461328 ps
CPU time 4.05 seconds
Started Aug 19 06:02:00 PM PDT 24
Finished Aug 19 06:02:04 PM PDT 24
Peak memory 220820 kb
Host smart-557efe11-7736-404a-a8d5-4692458c3e98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325843704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1325843704
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2976084793
Short name T81
Test name
Test status
Simulation time 234849296 ps
CPU time 1.2 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:01 PM PDT 24
Peak memory 237100 kb
Host smart-ba733497-93cc-4820-a8df-d9c353807d17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976084793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2976084793
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2001455943
Short name T328
Test name
Test status
Simulation time 16180085367 ps
CPU time 69.22 seconds
Started Aug 19 06:02:01 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 252336 kb
Host smart-8c044b77-3eed-4657-b870-54771ad061a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001455943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2001455943
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.851405616
Short name T311
Test name
Test status
Simulation time 1180645252 ps
CPU time 13.4 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 219468 kb
Host smart-305ebc99-3995-4493-a3c5-b2e8fa9119fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851405616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.851405616
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3969544191
Short name T497
Test name
Test status
Simulation time 70500010 ps
CPU time 0.99 seconds
Started Aug 19 06:01:56 PM PDT 24
Finished Aug 19 06:01:57 PM PDT 24
Peak memory 208136 kb
Host smart-7be70f4a-7250-4256-90ac-cbe419ac1997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969544191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3969544191
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3961857539
Short name T391
Test name
Test status
Simulation time 53055584 ps
CPU time 0.72 seconds
Started Aug 19 06:01:57 PM PDT 24
Finished Aug 19 06:01:58 PM PDT 24
Peak memory 206160 kb
Host smart-9bc4105b-bbec-4c5b-8a9c-21fd1e4c7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961857539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3961857539
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.493729416
Short name T181
Test name
Test status
Simulation time 9641611559 ps
CPU time 21.26 seconds
Started Aug 19 06:01:59 PM PDT 24
Finished Aug 19 06:02:21 PM PDT 24
Peak memory 224768 kb
Host smart-a54e67ff-b1a5-494b-b5bb-91cf24e4f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493729416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.493729416
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3551829774
Short name T445
Test name
Test status
Simulation time 19947163 ps
CPU time 0.71 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 205916 kb
Host smart-7c8855c1-3820-4fdc-ab6a-a811cc28e47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551829774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3551829774
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.362478408
Short name T669
Test name
Test status
Simulation time 406242687 ps
CPU time 5.12 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:03:14 PM PDT 24
Peak memory 232948 kb
Host smart-a2ba4e5f-375c-448b-bd1c-bc5944bf7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362478408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.362478408
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1369378437
Short name T615
Test name
Test status
Simulation time 66719148 ps
CPU time 0.76 seconds
Started Aug 19 06:03:10 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 206632 kb
Host smart-7ffcf81d-0180-43d4-8ba1-4d38b5e8bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369378437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1369378437
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1630450344
Short name T241
Test name
Test status
Simulation time 10552636082 ps
CPU time 21.16 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:03:30 PM PDT 24
Peak memory 249096 kb
Host smart-19384e1f-d961-4e45-8acf-8c0fcc406af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630450344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1630450344
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2882106007
Short name T272
Test name
Test status
Simulation time 20542976976 ps
CPU time 49.21 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:57 PM PDT 24
Peak memory 234092 kb
Host smart-b4808c7d-2469-4832-a9cb-9a398443e60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882106007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2882106007
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3734621078
Short name T683
Test name
Test status
Simulation time 526426452 ps
CPU time 4.94 seconds
Started Aug 19 06:03:11 PM PDT 24
Finished Aug 19 06:03:16 PM PDT 24
Peak memory 217768 kb
Host smart-e6fee020-f34c-4331-b118-7acc272e5b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734621078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3734621078
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.562513891
Short name T958
Test name
Test status
Simulation time 3441271412 ps
CPU time 16.69 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:03:25 PM PDT 24
Peak memory 236320 kb
Host smart-652d92f7-959e-45d0-8528-3517022592bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562513891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.562513891
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3175327362
Short name T385
Test name
Test status
Simulation time 91923906797 ps
CPU time 160.57 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:05:48 PM PDT 24
Peak memory 252748 kb
Host smart-caca6576-65f9-4592-b646-3617f11d2df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175327362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3175327362
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4274130470
Short name T220
Test name
Test status
Simulation time 12941771080 ps
CPU time 19.95 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 224740 kb
Host smart-aa35410d-ec8a-4e3e-b4b0-c63b7aa05e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274130470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4274130470
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3864691225
Short name T998
Test name
Test status
Simulation time 61960195 ps
CPU time 2.52 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 232920 kb
Host smart-2fb9acc3-2743-418c-80a2-5b6a46115edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864691225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3864691225
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.720808978
Short name T269
Test name
Test status
Simulation time 310090987 ps
CPU time 2.3 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 224648 kb
Host smart-38d41685-1318-4131-8979-225b687e906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720808978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.720808978
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.742056087
Short name T68
Test name
Test status
Simulation time 70669572 ps
CPU time 2.11 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 224636 kb
Host smart-61c2faea-ae52-40b4-93a6-2588683c77cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742056087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.742056087
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3506735631
Short name T157
Test name
Test status
Simulation time 1540308217 ps
CPU time 8.03 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:16 PM PDT 24
Peak memory 222344 kb
Host smart-f3de5b1f-73a1-4717-9094-8d6be4882d6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3506735631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3506735631
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1168465834
Short name T406
Test name
Test status
Simulation time 16506938284 ps
CPU time 125.63 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:05:14 PM PDT 24
Peak memory 256696 kb
Host smart-18ff5a0e-f203-4104-99af-3264a8d198c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168465834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1168465834
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1097888563
Short name T320
Test name
Test status
Simulation time 2739676901 ps
CPU time 20.18 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:26 PM PDT 24
Peak memory 216644 kb
Host smart-04135038-2149-47fd-bd60-3f50f06b8c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097888563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1097888563
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1501915083
Short name T849
Test name
Test status
Simulation time 13579940066 ps
CPU time 14.99 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:22 PM PDT 24
Peak memory 215424 kb
Host smart-1f55df8c-ccfa-4052-b019-db7409b69324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501915083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1501915083
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.606981775
Short name T701
Test name
Test status
Simulation time 125211195 ps
CPU time 1.37 seconds
Started Aug 19 06:03:11 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 216504 kb
Host smart-7c409e82-6201-45e5-bb6b-7682062d9d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606981775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.606981775
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3589694001
Short name T350
Test name
Test status
Simulation time 112334123 ps
CPU time 0.93 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 206136 kb
Host smart-2374a414-9cf3-4da1-91cc-5b61b32be4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589694001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3589694001
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4005303086
Short name T536
Test name
Test status
Simulation time 90587886 ps
CPU time 2.55 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 224684 kb
Host smart-3785c603-8669-4a1d-addc-e6bea4e90090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005303086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4005303086
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.883993330
Short name T613
Test name
Test status
Simulation time 15454239 ps
CPU time 0.71 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 204988 kb
Host smart-c5763c84-62c5-43df-af53-78ba979eec12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883993330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.883993330
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1120723444
Short name T453
Test name
Test status
Simulation time 8633366440 ps
CPU time 20.57 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:03:30 PM PDT 24
Peak memory 224808 kb
Host smart-80ab25be-7218-4ba3-9228-e5b75963f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120723444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1120723444
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.633234048
Short name T330
Test name
Test status
Simulation time 18683965 ps
CPU time 0.74 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 205608 kb
Host smart-b94011c6-43f8-49cd-a974-e6cc48444237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633234048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.633234048
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1879086414
Short name T39
Test name
Test status
Simulation time 80967044077 ps
CPU time 188.5 seconds
Started Aug 19 06:03:12 PM PDT 24
Finished Aug 19 06:06:20 PM PDT 24
Peak memory 270660 kb
Host smart-f79244be-8f38-4edf-b3ef-7572e6b1f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879086414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1879086414
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.514793757
Short name T568
Test name
Test status
Simulation time 41018129044 ps
CPU time 123.81 seconds
Started Aug 19 06:03:10 PM PDT 24
Finished Aug 19 06:05:14 PM PDT 24
Peak memory 249704 kb
Host smart-feaab5d1-b71e-4349-add9-c951110b72e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514793757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.514793757
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.552807896
Short name T575
Test name
Test status
Simulation time 4195723092 ps
CPU time 63.17 seconds
Started Aug 19 06:03:10 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 251944 kb
Host smart-e07ce274-f3d1-410d-b84d-06dcab8a7561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552807896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.552807896
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4051819661
Short name T144
Test name
Test status
Simulation time 632461406 ps
CPU time 2.59 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:11 PM PDT 24
Peak memory 224608 kb
Host smart-64c1668d-77ec-43b0-87e1-b056bcf6c275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051819661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4051819661
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2804140329
Short name T300
Test name
Test status
Simulation time 2275760591 ps
CPU time 19.83 seconds
Started Aug 19 06:03:12 PM PDT 24
Finished Aug 19 06:03:32 PM PDT 24
Peak memory 224796 kb
Host smart-a471987a-3c88-4816-b837-989a67d102fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804140329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2804140329
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3588158424
Short name T1029
Test name
Test status
Simulation time 487137836 ps
CPU time 2.67 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 232912 kb
Host smart-8c6761e6-d5a4-4c8b-b1d3-cf3490563f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588158424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3588158424
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.996106304
Short name T335
Test name
Test status
Simulation time 102810301 ps
CPU time 2.41 seconds
Started Aug 19 06:03:10 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 232536 kb
Host smart-fa273187-a14f-4cb4-b728-cc2d4e4bb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996106304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.996106304
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.409465012
Short name T706
Test name
Test status
Simulation time 570858189 ps
CPU time 4.37 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:12 PM PDT 24
Peak memory 232884 kb
Host smart-7b13a432-1295-4ce5-9fc1-b7b27e537b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409465012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.409465012
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2988927444
Short name T872
Test name
Test status
Simulation time 131142401 ps
CPU time 2.57 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:08 PM PDT 24
Peak memory 232928 kb
Host smart-5338ade6-2f23-449f-bdf6-5e2a3716eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988927444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2988927444
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.255388624
Short name T1009
Test name
Test status
Simulation time 1223963030 ps
CPU time 8.41 seconds
Started Aug 19 06:03:10 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 222248 kb
Host smart-1275b903-6b21-4795-b659-5a6cc074bd2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=255388624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.255388624
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3091662889
Short name T32
Test name
Test status
Simulation time 1612189802 ps
CPU time 35.22 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 235228 kb
Host smart-0b53dd10-7482-493e-b7f3-7c2812930187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091662889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3091662889
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.860599662
Short name T427
Test name
Test status
Simulation time 4069698775 ps
CPU time 22.32 seconds
Started Aug 19 06:03:11 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 220448 kb
Host smart-a15ff106-9f37-41c9-b784-689c35822ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860599662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.860599662
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2279383259
Short name T426
Test name
Test status
Simulation time 3606441013 ps
CPU time 12.76 seconds
Started Aug 19 06:03:07 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 216528 kb
Host smart-3cd49c4f-51db-4bef-a4ae-390ecb6934a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279383259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2279383259
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.272364633
Short name T814
Test name
Test status
Simulation time 29046031 ps
CPU time 0.93 seconds
Started Aug 19 06:03:09 PM PDT 24
Finished Aug 19 06:03:10 PM PDT 24
Peak memory 207172 kb
Host smart-9f37360d-b6df-4a3d-a2f3-d47958b3b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272364633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.272364633
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4108623056
Short name T367
Test name
Test status
Simulation time 37010728 ps
CPU time 0.74 seconds
Started Aug 19 06:03:08 PM PDT 24
Finished Aug 19 06:03:09 PM PDT 24
Peak memory 206152 kb
Host smart-8454fe51-acca-42e8-bf3c-b505f0c072d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108623056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4108623056
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3849496455
Short name T511
Test name
Test status
Simulation time 7741317094 ps
CPU time 27.54 seconds
Started Aug 19 06:03:06 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 249348 kb
Host smart-c2ede2ef-7a91-489d-914f-bfea708f3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849496455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3849496455
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2659775528
Short name T896
Test name
Test status
Simulation time 12512149 ps
CPU time 0.74 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:17 PM PDT 24
Peak memory 205920 kb
Host smart-b5993e3b-67ec-4c21-8dbb-1324a722931d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659775528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2659775528
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1838553608
Short name T250
Test name
Test status
Simulation time 156185022 ps
CPU time 2.77 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:19 PM PDT 24
Peak memory 224744 kb
Host smart-cc773e18-17db-4a5a-a49e-5580881c0208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838553608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1838553608
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.700827464
Short name T767
Test name
Test status
Simulation time 12264127 ps
CPU time 0.75 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:16 PM PDT 24
Peak memory 207008 kb
Host smart-a7bb0633-0925-47b9-9c92-2d59604ec736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700827464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.700827464
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3265768859
Short name T47
Test name
Test status
Simulation time 4946981543 ps
CPU time 69.28 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 249380 kb
Host smart-94682a2c-6e09-4f59-b937-44a5519821bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265768859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3265768859
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1282806396
Short name T618
Test name
Test status
Simulation time 3219577389 ps
CPU time 18.79 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:36 PM PDT 24
Peak memory 241232 kb
Host smart-dad9fc27-af98-444a-b372-88183b47ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282806396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1282806396
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.896476040
Short name T302
Test name
Test status
Simulation time 2167751446 ps
CPU time 17 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:32 PM PDT 24
Peak memory 224740 kb
Host smart-178534f3-e577-46c8-8f29-ba67161ec4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896476040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.896476040
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2405279277
Short name T908
Test name
Test status
Simulation time 1117532893 ps
CPU time 3.4 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 224672 kb
Host smart-2880f7db-bd4d-4742-abd1-4320a276eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405279277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2405279277
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.132185237
Short name T496
Test name
Test status
Simulation time 36438008117 ps
CPU time 154.38 seconds
Started Aug 19 06:03:19 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 233960 kb
Host smart-cc39ea96-3e25-4d45-b883-48da5961391a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132185237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.132185237
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2564126872
Short name T841
Test name
Test status
Simulation time 13370615606 ps
CPU time 13.22 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:29 PM PDT 24
Peak memory 224740 kb
Host smart-b634bd9f-3891-4a7a-81a1-5133f93bb995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564126872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2564126872
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1386765956
Short name T656
Test name
Test status
Simulation time 62408264 ps
CPU time 3.32 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 219452 kb
Host smart-95431028-746f-49fc-9013-49273049210f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1386765956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1386765956
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3620906390
Short name T843
Test name
Test status
Simulation time 3829073285 ps
CPU time 26.16 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 216544 kb
Host smart-b563053d-3f1a-4ea0-85c6-1e2b6e95e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620906390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3620906390
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3475467174
Short name T730
Test name
Test status
Simulation time 4223177202 ps
CPU time 3.67 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:21 PM PDT 24
Peak memory 216384 kb
Host smart-09e66d5a-dbc7-4747-9b90-9b7998acee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475467174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3475467174
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3743891039
Short name T873
Test name
Test status
Simulation time 182177226 ps
CPU time 1.4 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 216520 kb
Host smart-6b92acba-5163-442a-b6c4-e3d8062a5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743891039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3743891039
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.254213353
Short name T577
Test name
Test status
Simulation time 26156132 ps
CPU time 0.79 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:16 PM PDT 24
Peak memory 206148 kb
Host smart-f81b97c9-2433-494b-abea-76ed038bf757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254213353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.254213353
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4233075046
Short name T411
Test name
Test status
Simulation time 1395277672 ps
CPU time 2.58 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 224324 kb
Host smart-8acd0e97-77a5-487a-b70e-15704f0ca843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233075046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4233075046
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3483472920
Short name T892
Test name
Test status
Simulation time 47134072 ps
CPU time 0.69 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:15 PM PDT 24
Peak memory 205868 kb
Host smart-01892193-e183-4b60-b88b-4de7e5404c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483472920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3483472920
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4047640207
Short name T517
Test name
Test status
Simulation time 77858691 ps
CPU time 2.36 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:19 PM PDT 24
Peak memory 224620 kb
Host smart-84944d40-3f12-4cf7-96d1-541334c55f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047640207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4047640207
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.849865507
Short name T361
Test name
Test status
Simulation time 14004980 ps
CPU time 0.75 seconds
Started Aug 19 06:03:21 PM PDT 24
Finished Aug 19 06:03:22 PM PDT 24
Peak memory 205612 kb
Host smart-9410c558-27c2-4180-abd5-11f03fe906cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849865507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.849865507
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1077016433
Short name T976
Test name
Test status
Simulation time 531720438968 ps
CPU time 248.53 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:07:25 PM PDT 24
Peak memory 254028 kb
Host smart-7d444184-f2b4-4f9a-be92-259f389002f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077016433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1077016433
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4014753576
Short name T749
Test name
Test status
Simulation time 49935617533 ps
CPU time 276.81 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 249408 kb
Host smart-1cea0814-0211-43a5-bbb2-3966d46da429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014753576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4014753576
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1400450040
Short name T928
Test name
Test status
Simulation time 2948657013 ps
CPU time 20.8 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 224788 kb
Host smart-b837fb6a-8ee2-45e3-b914-456db79b64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400450040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1400450040
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.894563432
Short name T279
Test name
Test status
Simulation time 11611275388 ps
CPU time 45.79 seconds
Started Aug 19 06:03:21 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 236356 kb
Host smart-62386fdc-9e4c-4a3b-bf09-0cab5c1229ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894563432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.894563432
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.976359556
Short name T912
Test name
Test status
Simulation time 932793340 ps
CPU time 10.46 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:25 PM PDT 24
Peak memory 228128 kb
Host smart-44dbf5b5-7d6b-4eec-a664-c3fc0bad0c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976359556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.976359556
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2226918501
Short name T280
Test name
Test status
Simulation time 6893472927 ps
CPU time 24.46 seconds
Started Aug 19 06:03:23 PM PDT 24
Finished Aug 19 06:03:48 PM PDT 24
Peak memory 233016 kb
Host smart-932612b8-eae9-4167-8ed8-52fcc55a0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226918501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2226918501
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1340611569
Short name T682
Test name
Test status
Simulation time 49404627 ps
CPU time 2.28 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 224656 kb
Host smart-7d8ba753-8cdf-4c8f-9d42-47dab9622db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340611569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1340611569
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.546923838
Short name T901
Test name
Test status
Simulation time 1983574133 ps
CPU time 10.49 seconds
Started Aug 19 06:03:18 PM PDT 24
Finished Aug 19 06:03:29 PM PDT 24
Peak memory 232924 kb
Host smart-b92aabe2-36d6-4409-9c57-e0c76a5b1834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546923838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.546923838
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1457600840
Short name T855
Test name
Test status
Simulation time 6657539286 ps
CPU time 19.83 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 223248 kb
Host smart-0fa7b8da-1c31-47d9-9157-5c50c855b4e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457600840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1457600840
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1569311670
Short name T151
Test name
Test status
Simulation time 123245542051 ps
CPU time 1208.34 seconds
Started Aug 19 06:03:22 PM PDT 24
Finished Aug 19 06:23:31 PM PDT 24
Peak memory 273980 kb
Host smart-be89d4c6-28c2-4fd1-990b-ff444a57e4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569311670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1569311670
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3956157508
Short name T312
Test name
Test status
Simulation time 7571881624 ps
CPU time 21.98 seconds
Started Aug 19 06:03:14 PM PDT 24
Finished Aug 19 06:03:36 PM PDT 24
Peak memory 216552 kb
Host smart-b9b05851-3e8a-4a3c-93f8-876172f8caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956157508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3956157508
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.888866977
Short name T963
Test name
Test status
Simulation time 1090057709 ps
CPU time 4.39 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:21 PM PDT 24
Peak memory 216464 kb
Host smart-1698176b-0b32-48dc-af77-1107f2dfadeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888866977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.888866977
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2524653888
Short name T492
Test name
Test status
Simulation time 49475614 ps
CPU time 1.06 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:17 PM PDT 24
Peak memory 207172 kb
Host smart-0ef3f6d0-3343-474a-90cc-cf747d700403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524653888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2524653888
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3662236174
Short name T148
Test name
Test status
Simulation time 14622325 ps
CPU time 0.71 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:16 PM PDT 24
Peak memory 206144 kb
Host smart-87e3e2aa-c418-43f6-966f-24968de611ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662236174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3662236174
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.259982370
Short name T235
Test name
Test status
Simulation time 809598346 ps
CPU time 4.61 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:21 PM PDT 24
Peak memory 224680 kb
Host smart-0f40c4bd-9d73-4b85-b4c6-de2c32f4bd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259982370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.259982370
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3707827591
Short name T7
Test name
Test status
Simulation time 18763150 ps
CPU time 0.77 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 205488 kb
Host smart-8949e5c9-c50f-44f7-9fa0-a58ebe81aa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707827591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3707827591
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3248508759
Short name T779
Test name
Test status
Simulation time 2284441577 ps
CPU time 8.42 seconds
Started Aug 19 06:03:28 PM PDT 24
Finished Aug 19 06:03:36 PM PDT 24
Peak memory 232924 kb
Host smart-2a1bd5ed-3cbe-4853-bae9-d54867960c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248508759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3248508759
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.151339138
Short name T67
Test name
Test status
Simulation time 18320681 ps
CPU time 0.75 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 206624 kb
Host smart-ce3323fe-30a0-4aec-9c97-8732273390c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151339138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.151339138
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3944272162
Short name T1000
Test name
Test status
Simulation time 41837344143 ps
CPU time 171.95 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 256224 kb
Host smart-748819db-c8ee-4fe5-8069-0ce44704ef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944272162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3944272162
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2386351755
Short name T187
Test name
Test status
Simulation time 28106099104 ps
CPU time 281.95 seconds
Started Aug 19 06:03:32 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 259904 kb
Host smart-51a188a9-ff27-4d04-bf2b-b5a80d459098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386351755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2386351755
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.263085836
Short name T306
Test name
Test status
Simulation time 293804100 ps
CPU time 7.14 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 224728 kb
Host smart-850afa2d-3938-41ff-92ab-a50425c2c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263085836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.263085836
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.4106070517
Short name T38
Test name
Test status
Simulation time 1077847654 ps
CPU time 10.14 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:03:35 PM PDT 24
Peak memory 235360 kb
Host smart-da82fd3a-a8f7-4621-b9de-f34228ab660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106070517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.4106070517
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3183645868
Short name T993
Test name
Test status
Simulation time 891302193 ps
CPU time 3.76 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:21 PM PDT 24
Peak memory 232884 kb
Host smart-7f47d907-c68a-474c-99a4-732af9fe1805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183645868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3183645868
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.621337460
Short name T945
Test name
Test status
Simulation time 1128692114 ps
CPU time 4.68 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 224672 kb
Host smart-d8673edf-c1d8-48ff-b4f2-46be67b007b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621337460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.621337460
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2896675634
Short name T288
Test name
Test status
Simulation time 2425878520 ps
CPU time 5.25 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:23 PM PDT 24
Peak memory 224764 kb
Host smart-af250c4f-2899-4930-b530-ecd51b58a421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896675634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2896675634
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1869312911
Short name T583
Test name
Test status
Simulation time 203131594 ps
CPU time 2.37 seconds
Started Aug 19 06:03:23 PM PDT 24
Finished Aug 19 06:03:26 PM PDT 24
Peak memory 224680 kb
Host smart-bd6f44da-9892-4973-af3d-3092a07d67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869312911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1869312911
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2593704674
Short name T379
Test name
Test status
Simulation time 403679428 ps
CPU time 3.84 seconds
Started Aug 19 06:03:30 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 219844 kb
Host smart-91598729-d8bc-421e-9417-c0cecd429642
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2593704674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2593704674
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4110510495
Short name T169
Test name
Test status
Simulation time 96329610990 ps
CPU time 46.53 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 241220 kb
Host smart-12747fb8-99e9-4b13-9d03-9d100cd087df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110510495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4110510495
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2485237981
Short name T322
Test name
Test status
Simulation time 23409462063 ps
CPU time 16.57 seconds
Started Aug 19 06:03:17 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 216568 kb
Host smart-e0a85808-2204-4601-a5cf-222ff7561742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485237981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2485237981
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3540560229
Short name T631
Test name
Test status
Simulation time 9672538199 ps
CPU time 3 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:29 PM PDT 24
Peak memory 208204 kb
Host smart-a3a292f5-0d68-4eff-997f-cd257708d25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540560229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3540560229
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3935195500
Short name T664
Test name
Test status
Simulation time 268715439 ps
CPU time 8.06 seconds
Started Aug 19 06:03:19 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 216496 kb
Host smart-aa473ba5-91a8-4604-a5a2-7dc4be8b4e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935195500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3935195500
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2028840337
Short name T371
Test name
Test status
Simulation time 338467887 ps
CPU time 0.95 seconds
Started Aug 19 06:03:16 PM PDT 24
Finished Aug 19 06:03:17 PM PDT 24
Peak memory 206136 kb
Host smart-f8cf459d-9aee-41a8-8b1f-da46e26b705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028840337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2028840337
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.148706170
Short name T802
Test name
Test status
Simulation time 1215384567 ps
CPU time 2.95 seconds
Started Aug 19 06:03:15 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 224676 kb
Host smart-4767526b-58ba-422e-acee-926aafd260fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148706170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.148706170
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1562582263
Short name T483
Test name
Test status
Simulation time 13008012 ps
CPU time 0.73 seconds
Started Aug 19 06:03:23 PM PDT 24
Finished Aug 19 06:03:24 PM PDT 24
Peak memory 205560 kb
Host smart-a7f11ac4-21ac-496d-b05d-32d43b94e5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562582263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1562582263
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4151635350
Short name T690
Test name
Test status
Simulation time 424712220 ps
CPU time 3.35 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 232904 kb
Host smart-08c8fdf8-8fb3-45dc-ac98-c78a26195251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151635350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4151635350
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1848520950
Short name T1033
Test name
Test status
Simulation time 38211212 ps
CPU time 0.79 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:03:26 PM PDT 24
Peak memory 206616 kb
Host smart-12c47a81-a27f-471c-961f-f84eddbf1423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848520950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1848520950
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2107106489
Short name T760
Test name
Test status
Simulation time 53952068 ps
CPU time 0.79 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 215908 kb
Host smart-a1f2d807-87a1-47e4-b3d9-90d4d3d9c978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107106489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2107106489
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3001149474
Short name T809
Test name
Test status
Simulation time 25803107680 ps
CPU time 178.22 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:06:22 PM PDT 24
Peak memory 255728 kb
Host smart-89c710e2-afd3-4272-9661-0e450cc221f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001149474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3001149474
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2073308348
Short name T199
Test name
Test status
Simulation time 58501461637 ps
CPU time 525.45 seconds
Started Aug 19 06:03:29 PM PDT 24
Finished Aug 19 06:12:15 PM PDT 24
Peak memory 266836 kb
Host smart-f6ccc6b7-4a5d-4cf1-ab7a-fee30a58c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073308348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2073308348
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.83258649
Short name T756
Test name
Test status
Simulation time 3054877855 ps
CPU time 51.55 seconds
Started Aug 19 06:03:31 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 233024 kb
Host smart-b0309a4a-5b82-461b-a18f-7d0c782ca137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83258649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.83258649
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2777770738
Short name T757
Test name
Test status
Simulation time 5491061291 ps
CPU time 44.55 seconds
Started Aug 19 06:03:22 PM PDT 24
Finished Aug 19 06:04:06 PM PDT 24
Peak memory 241164 kb
Host smart-6416390d-4cd1-4581-8609-6cc3528badc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777770738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2777770738
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1379663012
Short name T965
Test name
Test status
Simulation time 442137390 ps
CPU time 6.47 seconds
Started Aug 19 06:03:28 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 232924 kb
Host smart-47f7a53f-a76d-4eab-996f-659baa445be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379663012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1379663012
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.886232104
Short name T1013
Test name
Test status
Simulation time 11356821346 ps
CPU time 26.28 seconds
Started Aug 19 06:03:32 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 224732 kb
Host smart-49aa3191-6692-4339-abfa-c11235bb1db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886232104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.886232104
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3864651868
Short name T266
Test name
Test status
Simulation time 423508483 ps
CPU time 2.74 seconds
Started Aug 19 06:03:30 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 224720 kb
Host smart-28d56d99-0792-46fd-b002-ff7b51206ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864651868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3864651868
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.344241
Short name T808
Test name
Test status
Simulation time 5239952123 ps
CPU time 14.12 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:03:38 PM PDT 24
Peak memory 232944 kb
Host smart-65b6ce67-fd76-4912-9f99-ae06fe4ad9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.344241
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1731800121
Short name T396
Test name
Test status
Simulation time 1033775472 ps
CPU time 5.78 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:32 PM PDT 24
Peak memory 220856 kb
Host smart-9bca58db-306a-47e2-8330-7a5d6aac78dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1731800121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1731800121
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2998736726
Short name T314
Test name
Test status
Simulation time 15419748652 ps
CPU time 9.29 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:36 PM PDT 24
Peak memory 216852 kb
Host smart-f2b16567-7a18-44df-9476-3ede3e83362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998736726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2998736726
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3716590634
Short name T698
Test name
Test status
Simulation time 600501362 ps
CPU time 4.84 seconds
Started Aug 19 06:03:29 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 216480 kb
Host smart-060a9ac0-45d6-42f7-aa2c-e76e78f01412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716590634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3716590634
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4268119020
Short name T458
Test name
Test status
Simulation time 33553732 ps
CPU time 1.21 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 208320 kb
Host smart-03f79849-9b82-42b8-ab29-27470ec5cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268119020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4268119020
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3475615462
Short name T341
Test name
Test status
Simulation time 64399477 ps
CPU time 0.8 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:03:26 PM PDT 24
Peak memory 206152 kb
Host smart-55cc6e25-5c88-4e25-8e52-90cc85fc6b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475615462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3475615462
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1744350914
Short name T925
Test name
Test status
Simulation time 606712522 ps
CPU time 4.69 seconds
Started Aug 19 06:03:30 PM PDT 24
Finished Aug 19 06:03:35 PM PDT 24
Peak memory 217244 kb
Host smart-f416f8d2-b542-4ade-8180-9d5c86e9611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744350914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1744350914
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1474831103
Short name T563
Test name
Test status
Simulation time 15031544 ps
CPU time 0.73 seconds
Started Aug 19 06:03:23 PM PDT 24
Finished Aug 19 06:03:24 PM PDT 24
Peak memory 205956 kb
Host smart-6d410785-482b-4b51-9ae0-4634975fd258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474831103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1474831103
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3367422948
Short name T944
Test name
Test status
Simulation time 2400044689 ps
CPU time 8 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 224816 kb
Host smart-f6959e4d-dc1e-41bd-b914-12ee90180f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367422948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3367422948
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2174675502
Short name T541
Test name
Test status
Simulation time 16234105 ps
CPU time 0.8 seconds
Started Aug 19 06:03:30 PM PDT 24
Finished Aug 19 06:03:31 PM PDT 24
Peak memory 206992 kb
Host smart-97eda973-fc5d-4cd2-97e7-c7bf5d206cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174675502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2174675502
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2913348371
Short name T146
Test name
Test status
Simulation time 11369460640 ps
CPU time 88.56 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 249456 kb
Host smart-3186e987-47bf-4578-b09a-7c945dc95bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913348371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2913348371
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4259206090
Short name T72
Test name
Test status
Simulation time 66525491398 ps
CPU time 68.74 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 253056 kb
Host smart-7cb38db2-1504-4384-b713-af30b0becc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259206090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4259206090
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.856471725
Short name T211
Test name
Test status
Simulation time 151560678431 ps
CPU time 329.47 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:08:55 PM PDT 24
Peak memory 251100 kb
Host smart-1b8bd4db-5a4e-4f6c-b0b0-153040f112d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856471725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.856471725
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1715840722
Short name T44
Test name
Test status
Simulation time 2642960513 ps
CPU time 37.33 seconds
Started Aug 19 06:03:25 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 241188 kb
Host smart-d0c43880-879e-40a8-81a2-402414c01f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715840722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1715840722
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2278608551
Short name T819
Test name
Test status
Simulation time 1723887816 ps
CPU time 8.92 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:03:33 PM PDT 24
Peak memory 224696 kb
Host smart-6001837d-ed26-4f68-bf16-eda3feac1290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278608551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2278608551
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1682632347
Short name T456
Test name
Test status
Simulation time 244475355 ps
CPU time 5.61 seconds
Started Aug 19 06:03:31 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 224692 kb
Host smart-79a6236b-93ab-4f11-8423-988297487089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682632347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1682632347
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1963300199
Short name T430
Test name
Test status
Simulation time 69893339 ps
CPU time 2.6 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:29 PM PDT 24
Peak memory 227776 kb
Host smart-5bc966a3-1e1a-4d04-996e-bdbe35302384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963300199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1963300199
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3564228850
Short name T939
Test name
Test status
Simulation time 812113820 ps
CPU time 2.35 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:29 PM PDT 24
Peak memory 224652 kb
Host smart-438c3d64-9f53-4c65-9884-156e0db45251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564228850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3564228850
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1961059180
Short name T862
Test name
Test status
Simulation time 60190679495 ps
CPU time 41.13 seconds
Started Aug 19 06:03:33 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 249376 kb
Host smart-0e381e02-1936-4532-9023-1b1c99c1e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961059180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1961059180
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1265410504
Short name T900
Test name
Test status
Simulation time 646240170 ps
CPU time 7.51 seconds
Started Aug 19 06:03:31 PM PDT 24
Finished Aug 19 06:03:39 PM PDT 24
Peak memory 222756 kb
Host smart-4b77773e-8ae9-4f2a-927b-22007fe68fae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265410504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1265410504
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1638007748
Short name T450
Test name
Test status
Simulation time 200479460 ps
CPU time 1.11 seconds
Started Aug 19 06:03:33 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 206912 kb
Host smart-06086c31-77a4-4116-a6dc-75b35e49402a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638007748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1638007748
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3052544955
Short name T586
Test name
Test status
Simulation time 7174884305 ps
CPU time 38.09 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:04:04 PM PDT 24
Peak memory 216556 kb
Host smart-edabe502-e680-4956-bafd-0c96372fc998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052544955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3052544955
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2857970566
Short name T850
Test name
Test status
Simulation time 3071074977 ps
CPU time 10.25 seconds
Started Aug 19 06:03:28 PM PDT 24
Finished Aug 19 06:03:39 PM PDT 24
Peak memory 216540 kb
Host smart-f0fc00c6-9096-4fe5-8d9f-13812fdc5563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857970566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2857970566
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.890181104
Short name T924
Test name
Test status
Simulation time 367260187 ps
CPU time 2.3 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 216488 kb
Host smart-3ca62740-c405-4204-b430-eb51032dd51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890181104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.890181104
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1371530131
Short name T91
Test name
Test status
Simulation time 235175440 ps
CPU time 0.87 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 206144 kb
Host smart-0b1b3ed4-087b-47e7-8440-262a2f020605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371530131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1371530131
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3851496369
Short name T588
Test name
Test status
Simulation time 3426474760 ps
CPU time 6.4 seconds
Started Aug 19 06:03:28 PM PDT 24
Finished Aug 19 06:03:35 PM PDT 24
Peak memory 224748 kb
Host smart-e14751f8-c834-42ba-a866-7f52cd29ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851496369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3851496369
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3774686958
Short name T927
Test name
Test status
Simulation time 48385870 ps
CPU time 0.72 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 205564 kb
Host smart-4bd0f1da-7c9d-48d6-9efb-868e187401fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774686958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3774686958
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3546955943
Short name T852
Test name
Test status
Simulation time 110536820 ps
CPU time 2.87 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:03:44 PM PDT 24
Peak memory 224740 kb
Host smart-1b3c37f7-139b-40d6-851b-76a92d8c0d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546955943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3546955943
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3158478990
Short name T806
Test name
Test status
Simulation time 101184276 ps
CPU time 0.78 seconds
Started Aug 19 06:03:27 PM PDT 24
Finished Aug 19 06:03:28 PM PDT 24
Peak memory 206980 kb
Host smart-e0c7fa02-fab3-4610-ab09-957bb2ecc1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158478990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3158478990
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3701286977
Short name T236
Test name
Test status
Simulation time 382758164173 ps
CPU time 215.02 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:07:19 PM PDT 24
Peak memory 265688 kb
Host smart-d3cf3dc9-7ada-4e67-972d-690647cc7024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701286977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3701286977
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2479901874
Short name T218
Test name
Test status
Simulation time 32855062623 ps
CPU time 129.46 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 249456 kb
Host smart-d9e4a91d-74b3-4732-bea1-b9cf89782866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479901874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2479901874
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3307529628
Short name T611
Test name
Test status
Simulation time 6607583178 ps
CPU time 32.04 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 224772 kb
Host smart-7475f57e-d853-4c9f-9d95-faba5ec67dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307529628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3307529628
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2190393895
Short name T574
Test name
Test status
Simulation time 112513447 ps
CPU time 2.42 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 232568 kb
Host smart-0a1cba4c-a568-4149-8cc8-9c38f9ea1019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190393895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2190393895
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2069257035
Short name T871
Test name
Test status
Simulation time 1723857423 ps
CPU time 11.49 seconds
Started Aug 19 06:03:44 PM PDT 24
Finished Aug 19 06:03:56 PM PDT 24
Peak memory 224664 kb
Host smart-2f5319e2-0827-4811-afd0-6bce5e0784d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069257035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2069257035
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1803784745
Short name T535
Test name
Test status
Simulation time 6046957550 ps
CPU time 10.58 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 224720 kb
Host smart-b22b2bde-0ff0-44e7-8cfa-fc2ade4a5483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803784745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1803784745
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1668204477
Short name T665
Test name
Test status
Simulation time 416925153 ps
CPU time 4.53 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:03:45 PM PDT 24
Peak memory 224680 kb
Host smart-c820f681-19bf-46c8-93b7-3ec4de8334be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668204477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1668204477
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2432033728
Short name T655
Test name
Test status
Simulation time 1202141193 ps
CPU time 12.29 seconds
Started Aug 19 06:03:40 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 222592 kb
Host smart-b806e7b6-9f19-4d5f-b254-80bd09213dbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432033728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2432033728
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3333935859
Short name T263
Test name
Test status
Simulation time 49428006534 ps
CPU time 96.03 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:05:19 PM PDT 24
Peak memory 252272 kb
Host smart-6d0ce191-eb48-47a1-8a7f-f4baeab716c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333935859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3333935859
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3810844174
Short name T521
Test name
Test status
Simulation time 7269154713 ps
CPU time 10.98 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:37 PM PDT 24
Peak memory 216568 kb
Host smart-0a270206-fbaa-4a07-9f08-54a9857cfdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810844174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3810844174
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4200348198
Short name T980
Test name
Test status
Simulation time 4471615274 ps
CPU time 9.54 seconds
Started Aug 19 06:03:24 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 216584 kb
Host smart-955fb1ff-51f9-4f30-a66e-55685aef6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200348198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4200348198
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.299124976
Short name T848
Test name
Test status
Simulation time 114799539 ps
CPU time 2.29 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:03:44 PM PDT 24
Peak memory 216540 kb
Host smart-870fde2d-19c8-4675-a145-6dc0e057694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299124976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.299124976
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4142703444
Short name T922
Test name
Test status
Simulation time 12638496 ps
CPU time 0.77 seconds
Started Aug 19 06:03:26 PM PDT 24
Finished Aug 19 06:03:27 PM PDT 24
Peak memory 205680 kb
Host smart-2b222ad8-e629-474f-aafa-0abfe38f64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142703444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4142703444
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3142848079
Short name T243
Test name
Test status
Simulation time 107315122 ps
CPU time 2.52 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 224656 kb
Host smart-959de8d0-e18b-48e2-8528-b78e4b74493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142848079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3142848079
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2686667071
Short name T951
Test name
Test status
Simulation time 33701731 ps
CPU time 0.69 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:44 PM PDT 24
Peak memory 205584 kb
Host smart-a2ce09e4-e840-464c-b26b-ebbbc0d7f873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686667071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2686667071
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.925080290
Short name T93
Test name
Test status
Simulation time 20514039045 ps
CPU time 10.31 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 224740 kb
Host smart-494f8f52-5131-42cc-b3fb-446c2dbd997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925080290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.925080290
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1423230988
Short name T1004
Test name
Test status
Simulation time 60153916 ps
CPU time 0.78 seconds
Started Aug 19 06:03:47 PM PDT 24
Finished Aug 19 06:03:48 PM PDT 24
Peak memory 206972 kb
Host smart-bd5f7d34-9d5e-4823-a2d8-14accc5c26fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423230988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1423230988
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1023283979
Short name T943
Test name
Test status
Simulation time 50273673955 ps
CPU time 117.24 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 250272 kb
Host smart-438c15a8-f477-4547-96be-3173208bfd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023283979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1023283979
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4071623412
Short name T447
Test name
Test status
Simulation time 6898570960 ps
CPU time 35.6 seconds
Started Aug 19 06:03:44 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 217808 kb
Host smart-3bbff834-2f60-4541-b64d-d85a9cdb8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071623412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4071623412
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3194509277
Short name T225
Test name
Test status
Simulation time 11229767527 ps
CPU time 180.6 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:06:43 PM PDT 24
Peak memory 266104 kb
Host smart-72b1ff46-c616-48f0-ba3f-68caa57f6684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194509277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3194509277
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1629330305
Short name T1019
Test name
Test status
Simulation time 325753937 ps
CPU time 10.03 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:03:56 PM PDT 24
Peak memory 240708 kb
Host smart-6d86cfbf-f140-4866-b4a5-14584c28062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629330305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1629330305
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3587723004
Short name T246
Test name
Test status
Simulation time 3960828606 ps
CPU time 51.12 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:04:37 PM PDT 24
Peak memory 254584 kb
Host smart-08be1237-70c7-41fd-9f9b-3b18e37f9d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587723004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3587723004
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3397713092
Short name T859
Test name
Test status
Simulation time 193549278 ps
CPU time 5.9 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:49 PM PDT 24
Peak memory 232904 kb
Host smart-ece910b7-53c5-4729-b2a5-4771515ff691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397713092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3397713092
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4142538911
Short name T713
Test name
Test status
Simulation time 4919546281 ps
CPU time 33.85 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 232924 kb
Host smart-4c56d3a3-44f4-45e1-9ac1-4c282a2df84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142538911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4142538911
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.723526209
Short name T752
Test name
Test status
Simulation time 3673938398 ps
CPU time 5.79 seconds
Started Aug 19 06:03:47 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 224736 kb
Host smart-f8513ba4-c46f-4ff6-aeab-48bdffd4283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723526209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.723526209
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.684176028
Short name T721
Test name
Test status
Simulation time 2227265380 ps
CPU time 2.43 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 224744 kb
Host smart-ba58905f-3ed9-4e93-967c-657aad91dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684176028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.684176028
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.711025702
Short name T386
Test name
Test status
Simulation time 196104636 ps
CPU time 3.93 seconds
Started Aug 19 06:03:39 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 218936 kb
Host smart-7f2c1fba-f1d0-4a3a-868c-570de3ff1938
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711025702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.711025702
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1218679827
Short name T499
Test name
Test status
Simulation time 39938296819 ps
CPU time 22.18 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:04:05 PM PDT 24
Peak memory 216556 kb
Host smart-c745bba7-dbee-46ed-893b-7c4075c1a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218679827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1218679827
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4246304260
Short name T372
Test name
Test status
Simulation time 6428386312 ps
CPU time 14.15 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 216572 kb
Host smart-858f6635-8c08-4d05-a1f5-5cfb70df2a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246304260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4246304260
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.505776603
Short name T384
Test name
Test status
Simulation time 147975663 ps
CPU time 2 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:03:45 PM PDT 24
Peak memory 216532 kb
Host smart-fe9a142e-ead1-49ba-94e3-f4987f35fd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505776603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.505776603
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1035556367
Short name T601
Test name
Test status
Simulation time 419539332 ps
CPU time 0.97 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:03:47 PM PDT 24
Peak memory 206144 kb
Host smart-d01ce689-8e71-4d11-bdef-91b7ae6d5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035556367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1035556367
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3372550166
Short name T475
Test name
Test status
Simulation time 12958198080 ps
CPU time 13.07 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:04:00 PM PDT 24
Peak memory 236508 kb
Host smart-7b0c10d7-6e66-496b-8183-a446edbb88ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372550166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3372550166
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.455867038
Short name T688
Test name
Test status
Simulation time 106433768 ps
CPU time 0.76 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 205576 kb
Host smart-ec01825c-1593-480b-b364-7cc03d575590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455867038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.455867038
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1998203271
Short name T459
Test name
Test status
Simulation time 435870977 ps
CPU time 4.94 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:48 PM PDT 24
Peak memory 232872 kb
Host smart-4aba3688-c819-45fc-8ba9-56bfb1bd9752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998203271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1998203271
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3852658644
Short name T686
Test name
Test status
Simulation time 46893238 ps
CPU time 0.82 seconds
Started Aug 19 06:03:44 PM PDT 24
Finished Aug 19 06:03:45 PM PDT 24
Peak memory 206780 kb
Host smart-fc50ce8f-5d90-4fbf-b807-2573f0255749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852658644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3852658644
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1830959975
Short name T640
Test name
Test status
Simulation time 2434589721 ps
CPU time 17.35 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 241196 kb
Host smart-602e1ccb-301c-493e-a942-a5432855e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830959975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1830959975
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.330458855
Short name T899
Test name
Test status
Simulation time 7780453831 ps
CPU time 106.18 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:05:29 PM PDT 24
Peak memory 265580 kb
Host smart-dde2b33f-a061-4735-9169-4a615bd4b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330458855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.330458855
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2177853132
Short name T646
Test name
Test status
Simulation time 7867200610 ps
CPU time 119.93 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 256968 kb
Host smart-19d87efa-337c-439c-b05f-7fa06523e413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177853132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2177853132
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1157134201
Short name T451
Test name
Test status
Simulation time 6161705371 ps
CPU time 32.26 seconds
Started Aug 19 06:03:46 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 224792 kb
Host smart-da360e1d-cb26-4ac5-b57d-12ed23a39e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157134201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1157134201
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1618916414
Short name T268
Test name
Test status
Simulation time 41848432899 ps
CPU time 304.93 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:08:48 PM PDT 24
Peak memory 264812 kb
Host smart-feb3fe10-e78a-430e-8d18-8cb36f152df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618916414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1618916414
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1124990778
Short name T395
Test name
Test status
Simulation time 115637092 ps
CPU time 2.3 seconds
Started Aug 19 06:03:44 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 232704 kb
Host smart-eb390bea-0231-4d60-8aba-888b348bb37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124990778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1124990778
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3093318061
Short name T811
Test name
Test status
Simulation time 2293126054 ps
CPU time 15.92 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 232964 kb
Host smart-b0cee6d0-5a5d-4041-a209-33ac1d606ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093318061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3093318061
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1302700187
Short name T48
Test name
Test status
Simulation time 5110004979 ps
CPU time 10.94 seconds
Started Aug 19 06:03:40 PM PDT 24
Finished Aug 19 06:03:51 PM PDT 24
Peak memory 232944 kb
Host smart-258ef3b5-5511-4dc6-969c-faf129f5103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302700187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1302700187
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2663581972
Short name T946
Test name
Test status
Simulation time 464782251 ps
CPU time 8.64 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:52 PM PDT 24
Peak memory 241004 kb
Host smart-4447e31f-ab33-4734-bccc-4a4e02e49a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663581972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2663581972
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4222398351
Short name T810
Test name
Test status
Simulation time 895504129 ps
CPU time 8.07 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:03:50 PM PDT 24
Peak memory 219132 kb
Host smart-b82a9e73-eb09-42c3-ab04-ac6bf2d0f4ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4222398351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4222398351
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2283585673
Short name T793
Test name
Test status
Simulation time 41532218935 ps
CPU time 109.19 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 266104 kb
Host smart-3fe0cd79-7e8e-4bc8-8fc5-6e30e4f836da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283585673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2283585673
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1358744087
Short name T724
Test name
Test status
Simulation time 723728975 ps
CPU time 5.17 seconds
Started Aug 19 06:03:45 PM PDT 24
Finished Aug 19 06:03:50 PM PDT 24
Peak memory 216476 kb
Host smart-e4d8e52b-b673-47ea-9217-1f7d395c31db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358744087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1358744087
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.154852251
Short name T830
Test name
Test status
Simulation time 4183610331 ps
CPU time 11.03 seconds
Started Aug 19 06:03:41 PM PDT 24
Finished Aug 19 06:03:52 PM PDT 24
Peak memory 216608 kb
Host smart-a8719cc0-5544-454e-8329-3e44b8df0036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154852251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.154852251
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2893914135
Short name T691
Test name
Test status
Simulation time 176329056 ps
CPU time 1.86 seconds
Started Aug 19 06:03:43 PM PDT 24
Finished Aug 19 06:03:45 PM PDT 24
Peak memory 216548 kb
Host smart-a6089fde-42d3-4e1e-88d0-2b3b8ea0e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893914135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2893914135
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1386014399
Short name T381
Test name
Test status
Simulation time 32300983 ps
CPU time 0.86 seconds
Started Aug 19 06:03:44 PM PDT 24
Finished Aug 19 06:03:44 PM PDT 24
Peak memory 207176 kb
Host smart-d7afc44f-1fb7-4f97-95dd-5f3116429b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386014399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1386014399
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2785988378
Short name T970
Test name
Test status
Simulation time 213330382 ps
CPU time 5 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:03:47 PM PDT 24
Peak memory 232848 kb
Host smart-7bfb734e-ca3b-49a6-9f9d-36f1d25d87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785988378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2785988378
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2542421330
Short name T693
Test name
Test status
Simulation time 28641029 ps
CPU time 0.71 seconds
Started Aug 19 06:02:07 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 204940 kb
Host smart-5c7b7cdf-043c-47cf-8caa-4e0950fb27eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542421330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
542421330
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1675274227
Short name T3
Test name
Test status
Simulation time 48746389 ps
CPU time 2.57 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 232924 kb
Host smart-3139a7ea-8b97-48f1-8c4d-8b7a6fb00ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675274227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1675274227
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3876999620
Short name T353
Test name
Test status
Simulation time 53009008 ps
CPU time 0.8 seconds
Started Aug 19 06:02:01 PM PDT 24
Finished Aug 19 06:02:02 PM PDT 24
Peak memory 206932 kb
Host smart-f160ed6f-a533-4c65-ba57-503c19183233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876999620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3876999620
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2068105441
Short name T70
Test name
Test status
Simulation time 3317340155 ps
CPU time 43.65 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:49 PM PDT 24
Peak memory 237572 kb
Host smart-1ad15887-893a-483e-ae32-04543cf8a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068105441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2068105441
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1148586294
Short name T857
Test name
Test status
Simulation time 19550074408 ps
CPU time 117.57 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 249444 kb
Host smart-826d99d8-99be-41eb-b8df-dfdf4d965d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148586294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1148586294
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3113922108
Short name T650
Test name
Test status
Simulation time 31649437943 ps
CPU time 288.43 seconds
Started Aug 19 06:02:09 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 252044 kb
Host smart-31bb63ad-6e88-43d0-bb6f-69b0ab5b400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113922108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3113922108
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3242689993
Short name T14
Test name
Test status
Simulation time 197038377 ps
CPU time 5.75 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:10 PM PDT 24
Peak memory 224708 kb
Host smart-4c40c2d6-40ff-41e1-a278-4d241bff2c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242689993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3242689993
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3932041727
Short name T293
Test name
Test status
Simulation time 15636815357 ps
CPU time 159.41 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:04:44 PM PDT 24
Peak memory 268416 kb
Host smart-e6afce16-ef13-40f9-ace3-ac032586da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932041727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3932041727
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3600545095
Short name T53
Test name
Test status
Simulation time 162662069 ps
CPU time 4.01 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 232948 kb
Host smart-96b88ddc-bf4d-448c-b32f-d8c8189e7ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600545095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3600545095
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.649251526
Short name T684
Test name
Test status
Simulation time 4379979540 ps
CPU time 32.2 seconds
Started Aug 19 06:02:03 PM PDT 24
Finished Aug 19 06:02:36 PM PDT 24
Peak memory 232992 kb
Host smart-2c299fe0-7c18-428a-89a3-3cf4ea7c0a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649251526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.649251526
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1985844522
Short name T512
Test name
Test status
Simulation time 58921698 ps
CPU time 1.05 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 216696 kb
Host smart-99551ffd-e32b-4280-bbf6-45cecd26a6ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985844522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1985844522
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2113258323
Short name T923
Test name
Test status
Simulation time 13801384869 ps
CPU time 21.59 seconds
Started Aug 19 06:02:07 PM PDT 24
Finished Aug 19 06:02:28 PM PDT 24
Peak memory 232968 kb
Host smart-6cb0ff7a-e108-4a7b-90ce-391408bae152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113258323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2113258323
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3517684572
Short name T885
Test name
Test status
Simulation time 36659119 ps
CPU time 2.59 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:14 PM PDT 24
Peak memory 232896 kb
Host smart-aa18fe3d-6982-4d41-913c-bdafd03cb10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517684572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3517684572
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2399353084
Short name T898
Test name
Test status
Simulation time 908173844 ps
CPU time 9.82 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:16 PM PDT 24
Peak memory 219340 kb
Host smart-71451945-6120-4af7-bb00-5fe946f1b11b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399353084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2399353084
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4083333000
Short name T80
Test name
Test status
Simulation time 43364933 ps
CPU time 0.99 seconds
Started Aug 19 06:02:07 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 235632 kb
Host smart-07b96180-b824-4487-b919-7837ea421820
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083333000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4083333000
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3386695578
Short name T604
Test name
Test status
Simulation time 3947235395 ps
CPU time 20.93 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:35 PM PDT 24
Peak memory 241276 kb
Host smart-8174266e-b272-42de-aeb5-143d1a9088a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386695578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3386695578
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.639257063
Short name T177
Test name
Test status
Simulation time 2842441452 ps
CPU time 6.33 seconds
Started Aug 19 06:02:02 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 216768 kb
Host smart-f7c54fce-40a5-4f70-8894-ed0427ea9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639257063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.639257063
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2001020700
Short name T383
Test name
Test status
Simulation time 7843128197 ps
CPU time 8.3 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 216556 kb
Host smart-a8e26c73-9a52-4120-a40c-f2418c04cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001020700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2001020700
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2533370365
Short name T839
Test name
Test status
Simulation time 28822599 ps
CPU time 1.39 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 216472 kb
Host smart-ee6f56f5-a365-422f-95a9-a66c540b6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533370365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2533370365
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2299345568
Short name T874
Test name
Test status
Simulation time 62572542 ps
CPU time 0.8 seconds
Started Aug 19 06:02:03 PM PDT 24
Finished Aug 19 06:02:04 PM PDT 24
Peak memory 206152 kb
Host smart-6457463b-e65e-49bb-9e9c-8b87c50aab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299345568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2299345568
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1143476336
Short name T708
Test name
Test status
Simulation time 98958322 ps
CPU time 2.67 seconds
Started Aug 19 06:02:16 PM PDT 24
Finished Aug 19 06:02:18 PM PDT 24
Peak memory 232932 kb
Host smart-dccd0359-7502-4845-ab26-4ce1760b0bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143476336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1143476336
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1131032335
Short name T559
Test name
Test status
Simulation time 20104561 ps
CPU time 0.7 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 204940 kb
Host smart-987708c6-ae55-4159-b6b6-2e807d0fee45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131032335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1131032335
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.646525748
Short name T544
Test name
Test status
Simulation time 4399115324 ps
CPU time 23.93 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:21 PM PDT 24
Peak memory 232944 kb
Host smart-2d9caeca-005f-4cd9-98c9-5193553cd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646525748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.646525748
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1610150687
Short name T412
Test name
Test status
Simulation time 135739467 ps
CPU time 0.79 seconds
Started Aug 19 06:03:42 PM PDT 24
Finished Aug 19 06:03:43 PM PDT 24
Peak memory 206972 kb
Host smart-68c6bd18-893d-4ce3-8c30-347b3b946dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610150687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1610150687
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2740059510
Short name T764
Test name
Test status
Simulation time 163438899654 ps
CPU time 284.77 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:08:38 PM PDT 24
Peak memory 256292 kb
Host smart-99646683-752e-4fc7-ae14-8206d4b1e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740059510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2740059510
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2858621636
Short name T388
Test name
Test status
Simulation time 3085739106 ps
CPU time 14.9 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:04:04 PM PDT 24
Peak memory 234512 kb
Host smart-3e19f0e7-22e5-446c-8371-dd225b372d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858621636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2858621636
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2631422375
Short name T818
Test name
Test status
Simulation time 8375203156 ps
CPU time 85.64 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:05:20 PM PDT 24
Peak memory 262692 kb
Host smart-11effa58-3408-4b8d-85b2-d767b8fd7ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631422375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2631422375
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2938905646
Short name T754
Test name
Test status
Simulation time 309480836 ps
CPU time 3.6 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:56 PM PDT 24
Peak memory 224668 kb
Host smart-e3f91b5b-bb6a-4ca2-823f-ea277ea0f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938905646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2938905646
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.952405878
Short name T230
Test name
Test status
Simulation time 1684441861 ps
CPU time 6.42 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:03 PM PDT 24
Peak memory 232856 kb
Host smart-091ea771-4136-48f6-87d7-33720d9de078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952405878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.952405878
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.609386925
Short name T889
Test name
Test status
Simulation time 4507636375 ps
CPU time 10.08 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 232956 kb
Host smart-712075e8-4b8c-4b37-ade1-f48fb361f916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609386925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.609386925
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2804908046
Short name T1023
Test name
Test status
Simulation time 5194028699 ps
CPU time 18.25 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 232904 kb
Host smart-d9a8c9aa-b696-492b-99b3-2627ce7aa3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804908046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2804908046
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3083365066
Short name T158
Test name
Test status
Simulation time 1318781607 ps
CPU time 16.06 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 220620 kb
Host smart-7ec4ecd3-52a1-4b7e-8def-5d45bfd64042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3083365066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3083365066
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2560472576
Short name T751
Test name
Test status
Simulation time 11408974547 ps
CPU time 79.61 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:05:12 PM PDT 24
Peak memory 250416 kb
Host smart-d1c6e7aa-cf32-4aae-900b-7e0c863d7459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560472576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2560472576
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.751501801
Short name T773
Test name
Test status
Simulation time 2025938418 ps
CPU time 15.98 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:04:05 PM PDT 24
Peak memory 216640 kb
Host smart-e866535d-ffb6-4edc-89ee-a50fc6a00eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751501801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.751501801
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2126361434
Short name T448
Test name
Test status
Simulation time 50806246097 ps
CPU time 18.71 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 216556 kb
Host smart-571a5394-dda9-4e99-9f9d-b4782e1dc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126361434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2126361434
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3217812506
Short name T13
Test name
Test status
Simulation time 130859739 ps
CPU time 1.14 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:03:55 PM PDT 24
Peak memory 208272 kb
Host smart-6fc487f3-e165-43e8-ae0c-7ecaca3477ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217812506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3217812506
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.615887121
Short name T606
Test name
Test status
Simulation time 26666075 ps
CPU time 0.78 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 206152 kb
Host smart-ea42438d-026b-4d12-a926-f0c213f3f9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615887121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.615887121
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.306079194
Short name T624
Test name
Test status
Simulation time 45353169556 ps
CPU time 26.2 seconds
Started Aug 19 06:03:47 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 241244 kb
Host smart-76feb2d1-7214-46fb-a090-b8a2aab69fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306079194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.306079194
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2510949390
Short name T464
Test name
Test status
Simulation time 47246768 ps
CPU time 0.73 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:03:50 PM PDT 24
Peak memory 204992 kb
Host smart-2a141f42-81f9-4d43-9e95-55bd16d7607f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510949390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2510949390
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3975172245
Short name T659
Test name
Test status
Simulation time 310256207 ps
CPU time 3.91 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 224676 kb
Host smart-c102e4c9-1d04-4aea-9ac8-19e30032da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975172245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3975172245
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2527033452
Short name T707
Test name
Test status
Simulation time 19198802 ps
CPU time 0.77 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:03:50 PM PDT 24
Peak memory 206948 kb
Host smart-af7fb4d2-7f92-4107-a329-1ca3108d2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527033452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2527033452
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2919532312
Short name T505
Test name
Test status
Simulation time 7902983995 ps
CPU time 59.24 seconds
Started Aug 19 06:03:51 PM PDT 24
Finished Aug 19 06:04:50 PM PDT 24
Peak memory 236428 kb
Host smart-b61fa6db-d5d2-4ca3-9a9a-cdb7f6b6668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919532312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2919532312
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3197448527
Short name T746
Test name
Test status
Simulation time 26812852094 ps
CPU time 91.84 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:05:24 PM PDT 24
Peak memory 265744 kb
Host smart-f31878d4-67a6-4492-90a2-ac6115d9fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197448527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3197448527
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1486643273
Short name T670
Test name
Test status
Simulation time 10642125421 ps
CPU time 33.48 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:27 PM PDT 24
Peak memory 253072 kb
Host smart-8ace3c37-38f4-42e2-b8b2-5a6dcbf79ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486643273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1486643273
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2388780983
Short name T282
Test name
Test status
Simulation time 871162896 ps
CPU time 10.01 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 232944 kb
Host smart-daf9e35c-f276-4c92-bc9a-d039f7af3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388780983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2388780983
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2309682835
Short name T488
Test name
Test status
Simulation time 2478164770 ps
CPU time 13.33 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 233960 kb
Host smart-3c7495e4-e70e-477a-b4d8-2171cb7965ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309682835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2309682835
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.333805994
Short name T510
Test name
Test status
Simulation time 6953047886 ps
CPU time 8.91 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 249004 kb
Host smart-47db585b-4527-4268-8f5b-c9a551a055b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333805994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.333805994
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.958992542
Short name T987
Test name
Test status
Simulation time 1751597950 ps
CPU time 6.04 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 224680 kb
Host smart-af8b7a4d-dbb1-4fac-8dc5-f5a43b82f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958992542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.958992542
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1701461864
Short name T741
Test name
Test status
Simulation time 2741953316 ps
CPU time 9.62 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:06 PM PDT 24
Peak memory 222852 kb
Host smart-9234fcc2-86b0-4f06-9036-40ce2f05a418
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701461864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1701461864
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1937095999
Short name T247
Test name
Test status
Simulation time 8590004768 ps
CPU time 46.5 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:41 PM PDT 24
Peak memory 239072 kb
Host smart-9acc616c-8802-44b8-b98f-6eb414b65b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937095999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1937095999
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4115524009
Short name T950
Test name
Test status
Simulation time 6897835495 ps
CPU time 19.57 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 216580 kb
Host smart-ac4e30c0-56ab-459f-88bc-e496d8d40220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115524009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4115524009
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2688081471
Short name T407
Test name
Test status
Simulation time 820509427 ps
CPU time 6.2 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:03:55 PM PDT 24
Peak memory 216468 kb
Host smart-12355a1d-ecb5-4143-8c39-6687a65ea537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688081471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2688081471
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2379884567
Short name T909
Test name
Test status
Simulation time 261324360 ps
CPU time 3.49 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 216440 kb
Host smart-95e37fe7-0d85-4c8d-ae09-5f48ac8d6741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379884567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2379884567
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1786048619
Short name T948
Test name
Test status
Simulation time 101188944 ps
CPU time 0.9 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 206144 kb
Host smart-751aa177-a2f8-4fc7-a35e-1135a2f61765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786048619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1786048619
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.265186631
Short name T856
Test name
Test status
Simulation time 3139369514 ps
CPU time 9.15 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:03 PM PDT 24
Peak memory 232952 kb
Host smart-2dd99f20-c833-4dfc-a01e-a6a5d3577b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265186631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.265186631
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1168164759
Short name T654
Test name
Test status
Simulation time 12643468 ps
CPU time 0.71 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 205532 kb
Host smart-b35978bc-5fdd-4ca4-839f-cf98c5d07cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168164759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1168164759
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1367940984
Short name T799
Test name
Test status
Simulation time 452143306 ps
CPU time 3.82 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 224664 kb
Host smart-7b298fe5-dfbe-4663-859d-94d5d5643b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367940984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1367940984
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4270196569
Short name T74
Test name
Test status
Simulation time 26577392 ps
CPU time 0.8 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 206964 kb
Host smart-6fafb2cd-67ee-4181-b2f2-b44c8af8b11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270196569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4270196569
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3417294431
Short name T905
Test name
Test status
Simulation time 961832372 ps
CPU time 11.77 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:06 PM PDT 24
Peak memory 236116 kb
Host smart-b4a635a1-004e-4d65-b0dc-dba6de9cd527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417294431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3417294431
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.408409392
Short name T571
Test name
Test status
Simulation time 3325869718 ps
CPU time 21.82 seconds
Started Aug 19 06:03:51 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 234508 kb
Host smart-a27857b6-f344-4676-b803-57142541bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408409392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.408409392
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2627828546
Short name T847
Test name
Test status
Simulation time 470061393 ps
CPU time 5.67 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 224676 kb
Host smart-7253b7ee-389b-4405-acac-e5322caaf3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627828546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2627828546
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.193571080
Short name T529
Test name
Test status
Simulation time 11749273 ps
CPU time 0.73 seconds
Started Aug 19 06:03:56 PM PDT 24
Finished Aug 19 06:03:57 PM PDT 24
Peak memory 215852 kb
Host smart-ef1aa3f5-c789-4232-951f-e5819628b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193571080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.193571080
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2539877366
Short name T1020
Test name
Test status
Simulation time 2263299610 ps
CPU time 19.91 seconds
Started Aug 19 06:03:49 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 220612 kb
Host smart-55ff3ad4-0a73-40c4-9d77-650b62d9a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539877366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2539877366
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2282090127
Short name T975
Test name
Test status
Simulation time 7904466452 ps
CPU time 10.3 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:04:04 PM PDT 24
Peak memory 232064 kb
Host smart-725a94d5-a844-46ca-b2a1-7ee634b014d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282090127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2282090127
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2372256629
Short name T982
Test name
Test status
Simulation time 2152166993 ps
CPU time 5.61 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:03:55 PM PDT 24
Peak memory 232980 kb
Host smart-e0f53a2a-03ca-41e5-b148-114c2323d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372256629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2372256629
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.541286805
Short name T262
Test name
Test status
Simulation time 58272172796 ps
CPU time 13.49 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 224736 kb
Host smart-6ccdb567-7400-4ac8-8d25-87b7bb91c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541286805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.541286805
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2050351103
Short name T1024
Test name
Test status
Simulation time 2838329148 ps
CPU time 10.22 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 222516 kb
Host smart-288e7808-88de-4d90-992d-50c0507e51f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2050351103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2050351103
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2420664458
Short name T780
Test name
Test status
Simulation time 8463631470 ps
CPU time 108.4 seconds
Started Aug 19 06:03:51 PM PDT 24
Finished Aug 19 06:05:39 PM PDT 24
Peak memory 250476 kb
Host smart-cda77c20-d684-4f33-9a40-bde6f19958f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420664458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2420664458
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2265884246
Short name T999
Test name
Test status
Simulation time 3997751902 ps
CPU time 15.66 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 216656 kb
Host smart-4879b457-f7d7-4b95-bf38-24a4c0a9643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265884246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2265884246
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1812910375
Short name T589
Test name
Test status
Simulation time 526772408 ps
CPU time 3.41 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:56 PM PDT 24
Peak memory 216512 kb
Host smart-0fb7f319-0d8a-4f31-b636-c5a3d4e2ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812910375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1812910375
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1443781084
Short name T507
Test name
Test status
Simulation time 155276981 ps
CPU time 2.89 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 216472 kb
Host smart-6eecaf3a-5376-4252-91b5-d6c28d6bb771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443781084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1443781084
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1826851583
Short name T546
Test name
Test status
Simulation time 65680741 ps
CPU time 0.71 seconds
Started Aug 19 06:03:54 PM PDT 24
Finished Aug 19 06:03:54 PM PDT 24
Peak memory 206088 kb
Host smart-e9496486-2584-46ae-a3be-145a37b23898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826851583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1826851583
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1299333283
Short name T449
Test name
Test status
Simulation time 3920588254 ps
CPU time 11.26 seconds
Started Aug 19 06:03:56 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 238204 kb
Host smart-99093c25-4955-4e43-88fb-871c406ddf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299333283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1299333283
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2552813432
Short name T365
Test name
Test status
Simulation time 23867598 ps
CPU time 0.72 seconds
Started Aug 19 06:03:51 PM PDT 24
Finished Aug 19 06:03:52 PM PDT 24
Peak memory 205544 kb
Host smart-82594f77-995c-4ff0-801f-d3bc6150aaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552813432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2552813432
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1505971157
Short name T978
Test name
Test status
Simulation time 54468716 ps
CPU time 2.09 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 224624 kb
Host smart-d5dff9ed-4fed-4dd3-b99f-cf0b09a12777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505971157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1505971157
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2953849584
Short name T573
Test name
Test status
Simulation time 52510838 ps
CPU time 0.78 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 206972 kb
Host smart-1a519bb2-4236-4d04-a19f-3687bc64cd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953849584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2953849584
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4022504856
Short name T735
Test name
Test status
Simulation time 232331590865 ps
CPU time 573.29 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:13:31 PM PDT 24
Peak memory 262084 kb
Host smart-df49df38-7f9e-4685-81e7-40113bb9d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022504856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4022504856
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2567331283
Short name T316
Test name
Test status
Simulation time 2793270642 ps
CPU time 21 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 241156 kb
Host smart-cc154be1-9340-4d5b-b194-dc17a7581d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567331283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2567331283
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3693150939
Short name T853
Test name
Test status
Simulation time 215457086 ps
CPU time 3.71 seconds
Started Aug 19 06:03:56 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 224704 kb
Host smart-43df75ab-b4e5-4eef-a072-5dafe489dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693150939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3693150939
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3996217572
Short name T258
Test name
Test status
Simulation time 255885641 ps
CPU time 3.65 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:04:02 PM PDT 24
Peak memory 232888 kb
Host smart-caf40851-1774-4db2-961a-6938e7634708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996217572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3996217572
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1549193657
Short name T771
Test name
Test status
Simulation time 505929039 ps
CPU time 11.42 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 232928 kb
Host smart-5a90b398-6e3d-4898-853a-46887158491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549193657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1549193657
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2983954235
Short name T678
Test name
Test status
Simulation time 8269096067 ps
CPU time 23.58 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 224792 kb
Host smart-f8353983-ea29-437a-bffc-1821be786f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983954235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2983954235
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2097547869
Short name T265
Test name
Test status
Simulation time 503799668 ps
CPU time 2.75 seconds
Started Aug 19 06:03:56 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 224624 kb
Host smart-3a6addcf-d849-4849-b93f-37caa85b7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097547869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2097547869
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1662132371
Short name T1021
Test name
Test status
Simulation time 1288418390 ps
CPU time 4.71 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 220132 kb
Host smart-8aa51c41-5030-4cff-9b90-dd4f4d565ef7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1662132371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1662132371
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1310091086
Short name T20
Test name
Test status
Simulation time 60628903 ps
CPU time 1.14 seconds
Started Aug 19 06:03:52 PM PDT 24
Finished Aug 19 06:03:53 PM PDT 24
Peak memory 206920 kb
Host smart-2941edd3-3f21-412c-bd60-338d3dc607fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310091086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1310091086
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3717043629
Short name T973
Test name
Test status
Simulation time 3347460534 ps
CPU time 24.39 seconds
Started Aug 19 06:03:50 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 216604 kb
Host smart-d12fa7da-6af4-4a75-893d-8164ccea4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717043629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3717043629
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3935806495
Short name T533
Test name
Test status
Simulation time 7527195266 ps
CPU time 19.75 seconds
Started Aug 19 06:03:53 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 216556 kb
Host smart-de5843de-5baf-47e7-a25a-015f0c432158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935806495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3935806495
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2038507116
Short name T482
Test name
Test status
Simulation time 102376193 ps
CPU time 0.92 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 206804 kb
Host smart-d0e4616a-3a4f-4c30-986e-edd162d95402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038507116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2038507116
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1699020350
Short name T345
Test name
Test status
Simulation time 57087153 ps
CPU time 0.67 seconds
Started Aug 19 06:03:51 PM PDT 24
Finished Aug 19 06:03:51 PM PDT 24
Peak memory 205652 kb
Host smart-a2c9c768-d426-4ce1-9d9a-6a8392683a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699020350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1699020350
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2174898226
Short name T186
Test name
Test status
Simulation time 2775082893 ps
CPU time 8.43 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:05 PM PDT 24
Peak memory 232892 kb
Host smart-6ed5b90f-4635-4956-93c4-249cf6912664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174898226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2174898226
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1877198342
Short name T428
Test name
Test status
Simulation time 13802044 ps
CPU time 0.75 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:08 PM PDT 24
Peak memory 204988 kb
Host smart-1b32de96-dd0a-4c3c-9d8f-0d84568ce5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877198342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1877198342
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2468217098
Short name T582
Test name
Test status
Simulation time 223336671 ps
CPU time 2.98 seconds
Started Aug 19 06:04:05 PM PDT 24
Finished Aug 19 06:04:08 PM PDT 24
Peak memory 224628 kb
Host smart-5c03e0f1-947a-4b94-be08-6fb46381de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468217098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2468217098
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.588672769
Short name T2
Test name
Test status
Simulation time 30282999 ps
CPU time 0.79 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:04:00 PM PDT 24
Peak memory 206984 kb
Host smart-48290213-3147-46b0-8c83-8a9c4f8caec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588672769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.588672769
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2891120137
Short name T984
Test name
Test status
Simulation time 27548468461 ps
CPU time 103.67 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 249376 kb
Host smart-b181c3ab-36ae-493e-8cb8-c5728ea019cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891120137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2891120137
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1740026507
Short name T409
Test name
Test status
Simulation time 69071108309 ps
CPU time 156.28 seconds
Started Aug 19 06:04:01 PM PDT 24
Finished Aug 19 06:06:37 PM PDT 24
Peak memory 252084 kb
Host smart-c9bbb563-062e-44b6-9651-68988b19433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740026507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1740026507
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1772617079
Short name T755
Test name
Test status
Simulation time 46058660337 ps
CPU time 107.48 seconds
Started Aug 19 06:04:05 PM PDT 24
Finished Aug 19 06:05:52 PM PDT 24
Peak memory 249408 kb
Host smart-e08cdb19-2a0c-4c14-a38c-213dc09a5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772617079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1772617079
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3656986983
Short name T83
Test name
Test status
Simulation time 21215380133 ps
CPU time 220.78 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 273000 kb
Host smart-303cac0a-1810-499d-8cef-812ae40af88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656986983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3656986983
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1751583879
Short name T747
Test name
Test status
Simulation time 67695481971 ps
CPU time 29.02 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:26 PM PDT 24
Peak memory 224788 kb
Host smart-b08015fb-0b17-41ec-a39a-a8a364b0d124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751583879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1751583879
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1287439915
Short name T672
Test name
Test status
Simulation time 779573193 ps
CPU time 3.73 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 224664 kb
Host smart-15bbd375-423c-49d0-a1a0-b9f5a8ba5a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287439915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1287439915
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1763303252
Short name T772
Test name
Test status
Simulation time 1632630685 ps
CPU time 12.77 seconds
Started Aug 19 06:04:04 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 233620 kb
Host smart-0427458d-5345-4082-9d6c-7327a93df90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763303252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1763303252
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.591120850
Short name T890
Test name
Test status
Simulation time 7414136767 ps
CPU time 26.73 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 224808 kb
Host smart-e573176b-7293-4713-a08d-e68552577245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591120850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.591120850
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2287871534
Short name T532
Test name
Test status
Simulation time 1185411793 ps
CPU time 12.72 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 221676 kb
Host smart-76d0b8df-217a-4792-822d-d2fadb68b3ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2287871534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2287871534
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1418718270
Short name T152
Test name
Test status
Simulation time 346299025214 ps
CPU time 812.44 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:17:32 PM PDT 24
Peak memory 272036 kb
Host smart-4bd049c5-d844-4313-862e-902d7bd75b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418718270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1418718270
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3417990703
Short name T485
Test name
Test status
Simulation time 3182344795 ps
CPU time 20.16 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 216588 kb
Host smart-a0482ed7-0e3e-4b2f-8259-2cca93ced902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417990703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3417990703
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1046526607
Short name T592
Test name
Test status
Simulation time 23165862 ps
CPU time 0.7 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 205752 kb
Host smart-526f97af-6cc6-42c9-bb12-17831bacffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046526607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1046526607
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3302991334
Short name T10
Test name
Test status
Simulation time 49430408 ps
CPU time 0.98 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:04:00 PM PDT 24
Peak memory 206552 kb
Host smart-6ce8327c-1f0d-4de4-b02b-08a2236a44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302991334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3302991334
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2725510255
Short name T503
Test name
Test status
Simulation time 603589297 ps
CPU time 0.81 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 206152 kb
Host smart-fb85aac1-04a8-47f4-8834-412ea002a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725510255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2725510255
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.912415533
Short name T628
Test name
Test status
Simulation time 939970471 ps
CPU time 7.6 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 239588 kb
Host smart-16a778e2-f873-4f9e-b309-1ecd9f339d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912415533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.912415533
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1469024062
Short name T674
Test name
Test status
Simulation time 10689727 ps
CPU time 0.7 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 205524 kb
Host smart-d919e39f-a45e-4ee4-8f72-70945bb70022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469024062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1469024062
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4287055806
Short name T443
Test name
Test status
Simulation time 295914718 ps
CPU time 2.08 seconds
Started Aug 19 06:04:04 PM PDT 24
Finished Aug 19 06:04:06 PM PDT 24
Peak memory 224444 kb
Host smart-be4a1866-d527-4b38-8f4a-0cf85946d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287055806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4287055806
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.520781185
Short name T865
Test name
Test status
Simulation time 22597960 ps
CPU time 0.82 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 206624 kb
Host smart-627e67f0-0aea-475f-a4a7-bff504298889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520781185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.520781185
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1223932960
Short name T738
Test name
Test status
Simulation time 3961566106 ps
CPU time 51.25 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:05:01 PM PDT 24
Peak memory 249360 kb
Host smart-1e34fbe2-9fbe-4fc5-b7e6-4ac6ffe99ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223932960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1223932960
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1993606338
Short name T893
Test name
Test status
Simulation time 44716128988 ps
CPU time 130.82 seconds
Started Aug 19 06:04:01 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 252020 kb
Host smart-ac99beba-6265-4fba-82e1-3c87a4576936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993606338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1993606338
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.650381868
Short name T992
Test name
Test status
Simulation time 44103955465 ps
CPU time 215.51 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:07:35 PM PDT 24
Peak memory 265656 kb
Host smart-c28cddca-a896-4f2d-819a-61b03a5a9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650381868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.650381868
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.447765972
Short name T308
Test name
Test status
Simulation time 729747639 ps
CPU time 19.63 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 232928 kb
Host smart-0c81ebc7-33b8-4b2b-8941-f86faf9b5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447765972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.447765972
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3341440945
Short name T100
Test name
Test status
Simulation time 5824958116 ps
CPU time 13.16 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 236760 kb
Host smart-dba364ac-ea8c-4c70-9a8d-a7fe7f48b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341440945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3341440945
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.524992793
Short name T257
Test name
Test status
Simulation time 492142045 ps
CPU time 5.42 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:04:04 PM PDT 24
Peak memory 224672 kb
Host smart-d272a849-97cd-40be-a5bc-fedf4863aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524992793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.524992793
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2095043063
Short name T596
Test name
Test status
Simulation time 12346176639 ps
CPU time 46.43 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 232936 kb
Host smart-cb58e231-df19-4dad-8d99-5c4934f8e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095043063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2095043063
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3030341677
Short name T1001
Test name
Test status
Simulation time 709668082 ps
CPU time 6.96 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 240980 kb
Host smart-8031e5ab-f90f-407e-ac93-9eb567f0d4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030341677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3030341677
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3919246761
Short name T545
Test name
Test status
Simulation time 1403388105 ps
CPU time 4.26 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 232868 kb
Host smart-54f8bc09-5124-475c-a5d1-e72000b3ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919246761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3919246761
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1361601994
Short name T988
Test name
Test status
Simulation time 1025560291 ps
CPU time 8.36 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 222264 kb
Host smart-653fcd1c-1b7e-41e5-8969-04f77153e556
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1361601994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1361601994
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2325739117
Short name T172
Test name
Test status
Simulation time 33634341340 ps
CPU time 113.22 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:05:51 PM PDT 24
Peak memory 255268 kb
Host smart-9c6051ff-6afc-4176-9dde-f661f319f0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325739117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2325739117
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3138344504
Short name T513
Test name
Test status
Simulation time 3125432363 ps
CPU time 16.38 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 216604 kb
Host smart-8240370a-0914-4c5b-bab3-275ccfc468a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138344504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3138344504
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4195926283
Short name T726
Test name
Test status
Simulation time 12222603385 ps
CPU time 9.96 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 216584 kb
Host smart-06b9f3b8-141d-4afb-9b3c-f6e3fc2a0290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195926283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4195926283
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.946453202
Short name T467
Test name
Test status
Simulation time 639995313 ps
CPU time 2.22 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 216528 kb
Host smart-8ef806bf-8068-4e64-a097-d4a3c4c72b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946453202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.946453202
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.74856004
Short name T479
Test name
Test status
Simulation time 69576373 ps
CPU time 0.9 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 207180 kb
Host smart-4586cd81-fd57-4bcc-aae1-4bf0d92b1161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74856004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.74856004
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3603097392
Short name T540
Test name
Test status
Simulation time 7020163363 ps
CPU time 16.54 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 232948 kb
Host smart-e5c3dc9f-4713-4819-82e8-bede7d2398ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603097392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3603097392
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2828745563
Short name T642
Test name
Test status
Simulation time 14438394 ps
CPU time 0.72 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:07 PM PDT 24
Peak memory 205492 kb
Host smart-38283c42-a14e-4d6d-8261-61e60d0ed71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828745563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2828745563
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1724306895
Short name T356
Test name
Test status
Simulation time 2158914746 ps
CPU time 16.52 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 232932 kb
Host smart-e508c9c6-ee48-46ba-bd67-9cc9f8704b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724306895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1724306895
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1737863173
Short name T329
Test name
Test status
Simulation time 19678277 ps
CPU time 0.84 seconds
Started Aug 19 06:04:00 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 206968 kb
Host smart-d227c0b8-17d9-4f55-bf6a-c4ba9bfc6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737863173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1737863173
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2602639424
Short name T264
Test name
Test status
Simulation time 1227350659605 ps
CPU time 456.33 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:11:48 PM PDT 24
Peak memory 270156 kb
Host smart-07f9a054-539b-4605-861b-84a9b056a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602639424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2602639424
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.54200425
Short name T883
Test name
Test status
Simulation time 66982516519 ps
CPU time 127.38 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 252700 kb
Host smart-8d091113-541a-4dc9-8266-1d1b7e496a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54200425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.54200425
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3574103888
Short name T188
Test name
Test status
Simulation time 31061316103 ps
CPU time 283.94 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:08:55 PM PDT 24
Peak memory 253708 kb
Host smart-754a35bb-c147-46cc-8f74-7dff068d2b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574103888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3574103888
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3593132410
Short name T1032
Test name
Test status
Simulation time 4463162144 ps
CPU time 62.83 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:05:13 PM PDT 24
Peak memory 249360 kb
Host smart-03fe686e-67ef-43ea-95b1-18080b48d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593132410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3593132410
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1004891433
Short name T370
Test name
Test status
Simulation time 1720532976 ps
CPU time 8.01 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 224692 kb
Host smart-43b4fb02-5e05-488d-b7d3-b894b7e74e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004891433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1004891433
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1438646576
Short name T842
Test name
Test status
Simulation time 2867642272 ps
CPU time 25.03 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 232932 kb
Host smart-c808092d-7cdf-4456-80c8-4a8658d5f43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438646576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1438646576
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2098022344
Short name T886
Test name
Test status
Simulation time 4912306162 ps
CPU time 21.55 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 240840 kb
Host smart-dfa944d4-dc13-42dd-a986-6f4deafee024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098022344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2098022344
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1172368775
Short name T543
Test name
Test status
Simulation time 1742116138 ps
CPU time 4.24 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 232924 kb
Host smart-fdf88d86-0051-4227-91e1-a87879ac04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172368775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1172368775
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1003797681
Short name T333
Test name
Test status
Simulation time 241688581 ps
CPU time 2.21 seconds
Started Aug 19 06:03:59 PM PDT 24
Finished Aug 19 06:04:01 PM PDT 24
Peak memory 232520 kb
Host smart-f57985fa-c0e3-4713-ac7a-300115598723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003797681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1003797681
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1903430121
Short name T534
Test name
Test status
Simulation time 1898300437 ps
CPU time 14.73 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 223088 kb
Host smart-6d6ff18c-5d01-4e1c-bfa3-0b4e253eca64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1903430121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1903430121
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1738731409
Short name T30
Test name
Test status
Simulation time 6785423474 ps
CPU time 46.44 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 241236 kb
Host smart-77c8128e-b1b5-482b-9652-452ed1c899e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738731409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1738731409
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3558324315
Short name T56
Test name
Test status
Simulation time 41028280018 ps
CPU time 45.41 seconds
Started Aug 19 06:04:05 PM PDT 24
Finished Aug 19 06:04:50 PM PDT 24
Peak memory 216556 kb
Host smart-f3932f62-16ee-4fff-a804-4759e56cd955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558324315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3558324315
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3852662489
Short name T519
Test name
Test status
Simulation time 3052829692 ps
CPU time 6.12 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 216556 kb
Host smart-666d2a47-a0c2-4841-af19-15cd14bb6189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852662489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3852662489
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.707599285
Short name T794
Test name
Test status
Simulation time 90572343 ps
CPU time 1 seconds
Started Aug 19 06:03:57 PM PDT 24
Finished Aug 19 06:03:58 PM PDT 24
Peak memory 207528 kb
Host smart-bcd93244-af53-4562-9e39-38eaafb2c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707599285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.707599285
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.10696185
Short name T569
Test name
Test status
Simulation time 28528017 ps
CPU time 0.78 seconds
Started Aug 19 06:03:58 PM PDT 24
Finished Aug 19 06:03:59 PM PDT 24
Peak memory 206096 kb
Host smart-3f098fac-98f1-4aac-b0c6-8064d07fd355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10696185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.10696185
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.899568599
Short name T758
Test name
Test status
Simulation time 1453152248 ps
CPU time 6.55 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 224676 kb
Host smart-2ccdcc10-e65a-4323-8d29-252e3f3f40a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899568599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.899568599
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1675510540
Short name T176
Test name
Test status
Simulation time 23445909 ps
CPU time 0.7 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 205904 kb
Host smart-b1d6907c-4bd5-4fbe-961e-45df26a14067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675510540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1675510540
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4095410900
Short name T180
Test name
Test status
Simulation time 157432029 ps
CPU time 2.5 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 232548 kb
Host smart-71a96ac3-88ce-4175-8c26-512fdbb8c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095410900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4095410900
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2083388397
Short name T720
Test name
Test status
Simulation time 53900882 ps
CPU time 0.77 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 207012 kb
Host smart-c0a30e37-d9f6-4ed2-a4c0-f4a0324810d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083388397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2083388397
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1749231116
Short name T558
Test name
Test status
Simulation time 41417389977 ps
CPU time 85.06 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:05:33 PM PDT 24
Peak memory 254648 kb
Host smart-38467274-dce2-4d01-8c80-9f9c4a37e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749231116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1749231116
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1845900550
Short name T71
Test name
Test status
Simulation time 4019972311 ps
CPU time 17.08 seconds
Started Aug 19 06:04:05 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 237972 kb
Host smart-8168c409-305c-4824-a9eb-d0e109138fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845900550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1845900550
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1979458384
Short name T796
Test name
Test status
Simulation time 1300635867 ps
CPU time 2.78 seconds
Started Aug 19 06:04:12 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 217772 kb
Host smart-4d18dab0-7c63-4c7d-a4e6-36d50ff70b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979458384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1979458384
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4256911490
Short name T303
Test name
Test status
Simulation time 1833333185 ps
CPU time 10.79 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 241132 kb
Host smart-dc531a39-17f3-4216-a4c6-97631c7a2dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256911490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4256911490
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3294736188
Short name T551
Test name
Test status
Simulation time 1207146163 ps
CPU time 6.41 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:27 PM PDT 24
Peak memory 238932 kb
Host smart-4fe45c8c-e9b9-49c7-9371-f48b83787350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294736188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3294736188
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1922232853
Short name T331
Test name
Test status
Simulation time 106323747 ps
CPU time 2.09 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:10 PM PDT 24
Peak memory 223180 kb
Host smart-b0a334a3-6efa-4ce1-9084-ac74fe7229e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922232853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1922232853
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2544639355
Short name T63
Test name
Test status
Simulation time 5584974819 ps
CPU time 21.86 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 232996 kb
Host smart-21e47315-5edc-489e-bcd6-1cfe6eb483f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544639355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2544639355
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1003684207
Short name T299
Test name
Test status
Simulation time 3666716826 ps
CPU time 4.73 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:16 PM PDT 24
Peak memory 233028 kb
Host smart-f83522d0-6bb2-4e0f-8aa0-f25ed185fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003684207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1003684207
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3230455025
Short name T956
Test name
Test status
Simulation time 3527043202 ps
CPU time 6.79 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 224764 kb
Host smart-5470fd2a-a997-45c8-9b31-ede4a4ed9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230455025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3230455025
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2953454284
Short name T680
Test name
Test status
Simulation time 271914422 ps
CPU time 3.69 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 220504 kb
Host smart-c7198407-cb59-43a9-b66e-e628f478d2e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953454284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2953454284
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1873310365
Short name T1026
Test name
Test status
Simulation time 51625185 ps
CPU time 0.93 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 206592 kb
Host smart-cc2edbdc-f4a0-48a4-b269-910f2d03e0d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873310365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1873310365
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.450819200
Short name T645
Test name
Test status
Simulation time 60856680940 ps
CPU time 49.26 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 216560 kb
Host smart-033d2ebe-c43a-49e8-a062-294fe411af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450819200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.450819200
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.784370050
Short name T777
Test name
Test status
Simulation time 4083289792 ps
CPU time 13.29 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 216608 kb
Host smart-b8763cca-3297-4e6e-9ba2-b60b8435cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784370050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.784370050
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1823366953
Short name T578
Test name
Test status
Simulation time 43619532 ps
CPU time 1.11 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:09 PM PDT 24
Peak memory 216500 kb
Host smart-b07a0dd4-d1c7-4be9-8534-e8bb46d76bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823366953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1823366953
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1761879707
Short name T498
Test name
Test status
Simulation time 25441575 ps
CPU time 0.77 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 206148 kb
Host smart-dac6e61d-fd14-4386-980b-4a57849290dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761879707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1761879707
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1924179012
Short name T697
Test name
Test status
Simulation time 1702063190 ps
CPU time 10.85 seconds
Started Aug 19 06:04:10 PM PDT 24
Finished Aug 19 06:04:21 PM PDT 24
Peak memory 232804 kb
Host smart-1d75d042-38fe-4999-8a2c-1f2c8329ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924179012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1924179012
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.362627099
Short name T360
Test name
Test status
Simulation time 13189975 ps
CPU time 0.71 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 204932 kb
Host smart-112e52d2-993e-4e03-8041-841efad07c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362627099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.362627099
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2811242003
Short name T880
Test name
Test status
Simulation time 165265161 ps
CPU time 2.86 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:14 PM PDT 24
Peak memory 232876 kb
Host smart-30e99428-8cd4-4923-9828-8dd3d3566bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811242003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2811242003
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2058102182
Short name T902
Test name
Test status
Simulation time 24929669 ps
CPU time 0.76 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:08 PM PDT 24
Peak memory 206976 kb
Host smart-6575e996-c0e6-4076-8320-234547478ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058102182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2058102182
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2366253640
Short name T515
Test name
Test status
Simulation time 17323349 ps
CPU time 0.75 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:08 PM PDT 24
Peak memory 215908 kb
Host smart-05e6e06f-4260-4737-85e3-0764fed993b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366253640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2366253640
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3984659482
Short name T838
Test name
Test status
Simulation time 64489023856 ps
CPU time 116.79 seconds
Started Aug 19 06:04:19 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 257492 kb
Host smart-624762a4-1022-4d7c-8d0a-98217933e8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984659482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3984659482
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1205403921
Short name T572
Test name
Test status
Simulation time 141730703 ps
CPU time 2.68 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 232876 kb
Host smart-600f2dd4-4d71-447f-8c9f-40a69b797d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205403921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1205403921
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1770429486
Short name T964
Test name
Test status
Simulation time 1836372502 ps
CPU time 19.28 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 239896 kb
Host smart-000df1e7-87e1-4279-b1b1-aa8a4dbf42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770429486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1770429486
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1618977345
Short name T711
Test name
Test status
Simulation time 898727381 ps
CPU time 9.74 seconds
Started Aug 19 06:04:12 PM PDT 24
Finished Aug 19 06:04:21 PM PDT 24
Peak memory 232928 kb
Host smart-ec3339bf-0b65-4398-89fa-f7e9f6836615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618977345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1618977345
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1607108041
Short name T675
Test name
Test status
Simulation time 9000148595 ps
CPU time 5.82 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 224788 kb
Host smart-cb5f489e-4da8-4528-8b6c-c407a08e3d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607108041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1607108041
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.907470510
Short name T274
Test name
Test status
Simulation time 726774757 ps
CPU time 7.32 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:16 PM PDT 24
Peak memory 240660 kb
Host smart-4d486204-0aa5-4aae-96ba-66f154ff2dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907470510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.907470510
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2395931332
Short name T227
Test name
Test status
Simulation time 659276002 ps
CPU time 5.26 seconds
Started Aug 19 06:04:05 PM PDT 24
Finished Aug 19 06:04:11 PM PDT 24
Peak memory 224732 kb
Host smart-bb553077-654b-4a0a-b68a-727a023d9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395931332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2395931332
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3223270080
Short name T614
Test name
Test status
Simulation time 12699399566 ps
CPU time 16.23 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 219260 kb
Host smart-dd685a37-bc4f-4c50-a502-749f8e7940bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223270080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3223270080
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.752279088
Short name T171
Test name
Test status
Simulation time 29599036149 ps
CPU time 199.53 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:07:31 PM PDT 24
Peak memory 250760 kb
Host smart-17a071fc-1b03-4b1c-b4e5-4201b6a7ac51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752279088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.752279088
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2851720237
Short name T57
Test name
Test status
Simulation time 914215185 ps
CPU time 13.23 seconds
Started Aug 19 06:04:09 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 216496 kb
Host smart-34f955ae-df32-4348-9c7d-f77b1a72c4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851720237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2851720237
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2071879608
Short name T663
Test name
Test status
Simulation time 6357020626 ps
CPU time 17.02 seconds
Started Aug 19 06:04:06 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 216604 kb
Host smart-32493d75-d5d1-4eab-be4d-109cd9fff302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071879608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2071879608
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4175045839
Short name T437
Test name
Test status
Simulation time 15075799 ps
CPU time 0.96 seconds
Started Aug 19 06:04:11 PM PDT 24
Finished Aug 19 06:04:12 PM PDT 24
Peak memory 207592 kb
Host smart-3f4da92c-c1cb-4ef7-b4a5-d800a212022b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175045839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4175045839
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.981719774
Short name T832
Test name
Test status
Simulation time 19391091 ps
CPU time 0.69 seconds
Started Aug 19 06:04:07 PM PDT 24
Finished Aug 19 06:04:08 PM PDT 24
Peak memory 205668 kb
Host smart-cba3d512-f1cc-4b97-b416-c87bee581a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981719774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.981719774
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.738260050
Short name T493
Test name
Test status
Simulation time 2657693653 ps
CPU time 7.13 seconds
Started Aug 19 06:04:08 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 233032 kb
Host smart-5c2163eb-2f1a-4144-8371-9db4a7940d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738260050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.738260050
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.858864722
Short name T894
Test name
Test status
Simulation time 12937327 ps
CPU time 0.87 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 205568 kb
Host smart-ac43bd0c-12fd-4454-a578-ffc5e9e0b027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858864722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.858864722
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.612552481
Short name T782
Test name
Test status
Simulation time 82314159 ps
CPU time 2.57 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:04:20 PM PDT 24
Peak memory 232924 kb
Host smart-72b277cb-f67e-457c-aebb-40c811f441d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612552481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.612552481
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4104824883
Short name T438
Test name
Test status
Simulation time 56507694 ps
CPU time 0.78 seconds
Started Aug 19 06:04:12 PM PDT 24
Finished Aug 19 06:04:13 PM PDT 24
Peak memory 206584 kb
Host smart-987e2ace-45b8-4088-b113-47856e150fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104824883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4104824883
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1438466356
Short name T823
Test name
Test status
Simulation time 44119039969 ps
CPU time 137.16 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 249936 kb
Host smart-c5e038ce-f63a-40f9-9ac9-9c6f25e5d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438466356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1438466356
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2407525300
Short name T237
Test name
Test status
Simulation time 12124988668 ps
CPU time 129.15 seconds
Started Aug 19 06:04:15 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 254904 kb
Host smart-54aeae49-eca5-4ed7-b549-3661686c8f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407525300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2407525300
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.28050229
Short name T632
Test name
Test status
Simulation time 48148874413 ps
CPU time 165.56 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:07:03 PM PDT 24
Peak memory 241116 kb
Host smart-20f82d79-f437-480e-911e-436594d31ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28050229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.28050229
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2765622076
Short name T1016
Test name
Test status
Simulation time 3838919454 ps
CPU time 10.98 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 224784 kb
Host smart-362ae658-e66f-4cda-a841-e503673d28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765622076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2765622076
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3620009968
Short name T561
Test name
Test status
Simulation time 39773687370 ps
CPU time 105.43 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:06:04 PM PDT 24
Peak memory 249380 kb
Host smart-b3811564-f20f-451a-8d8b-f121d2be23ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620009968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3620009968
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.192997613
Short name T785
Test name
Test status
Simulation time 446238524 ps
CPU time 5.72 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 232932 kb
Host smart-6c294bd5-fc5d-4d26-9d28-55f1ade0c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192997613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.192997613
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1760336544
Short name T918
Test name
Test status
Simulation time 8567713377 ps
CPU time 15.09 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:33 PM PDT 24
Peak memory 241104 kb
Host smart-d1e674fe-78ff-4ac5-b429-3d32d815f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760336544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1760336544
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.279098388
Short name T51
Test name
Test status
Simulation time 10051137376 ps
CPU time 7.2 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 234980 kb
Host smart-ab78d50d-644b-4411-81c8-d46cea81a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279098388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.279098388
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2382184920
Short name T651
Test name
Test status
Simulation time 94730114 ps
CPU time 2.75 seconds
Started Aug 19 06:04:22 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 232932 kb
Host smart-de38ded7-b246-454a-89cd-a1c00a2b7e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382184920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2382184920
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3136302425
Short name T1012
Test name
Test status
Simulation time 118897417 ps
CPU time 3.52 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 220072 kb
Host smart-f6469b75-3e25-45bf-9e22-b6c959c88dce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3136302425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3136302425
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4214481387
Short name T868
Test name
Test status
Simulation time 92989374 ps
CPU time 0.96 seconds
Started Aug 19 06:04:15 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 206964 kb
Host smart-7c173df3-260b-4739-87a1-8e941381d4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214481387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4214481387
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.575853228
Short name T310
Test name
Test status
Simulation time 2684967443 ps
CPU time 24.51 seconds
Started Aug 19 06:04:16 PM PDT 24
Finished Aug 19 06:04:41 PM PDT 24
Peak memory 216608 kb
Host smart-d7bd1dd6-2bc2-4c65-a9ec-b1ba317baad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575853228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.575853228
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2758700028
Short name T315
Test name
Test status
Simulation time 1121370647 ps
CPU time 4.58 seconds
Started Aug 19 06:04:22 PM PDT 24
Finished Aug 19 06:04:27 PM PDT 24
Peak memory 216472 kb
Host smart-a3ae2b57-2376-4601-bc3c-945ab312bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758700028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2758700028
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3281325336
Short name T405
Test name
Test status
Simulation time 94447530 ps
CPU time 1.71 seconds
Started Aug 19 06:04:16 PM PDT 24
Finished Aug 19 06:04:18 PM PDT 24
Peak memory 216544 kb
Host smart-ca95d14f-083a-4189-8a02-961c0422a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281325336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3281325336
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.524912074
Short name T961
Test name
Test status
Simulation time 78752887 ps
CPU time 1.11 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:21 PM PDT 24
Peak memory 207168 kb
Host smart-ea7e3908-c32f-4925-8633-329ecaea90c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524912074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.524912074
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1230852252
Short name T259
Test name
Test status
Simulation time 3713017459 ps
CPU time 4.91 seconds
Started Aug 19 06:04:22 PM PDT 24
Finished Aug 19 06:04:27 PM PDT 24
Peak memory 217428 kb
Host smart-7f5b59b6-b2cc-4d0d-a3af-054f646f1f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230852252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1230852252
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2351891150
Short name T349
Test name
Test status
Simulation time 22973564 ps
CPU time 0.7 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 205548 kb
Host smart-3611b768-79cd-4b28-b6e0-d69dbce74227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351891150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
351891150
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.983645612
Short name T1010
Test name
Test status
Simulation time 2440013603 ps
CPU time 7.29 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 224736 kb
Host smart-6618408e-97fa-4132-9fbf-df81c143917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983645612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.983645612
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3846646930
Short name T623
Test name
Test status
Simulation time 40232982 ps
CPU time 0.77 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 206620 kb
Host smart-cf6c72cb-522f-4715-be70-6aa8f09c1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846646930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3846646930
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2399458161
Short name T206
Test name
Test status
Simulation time 81861686430 ps
CPU time 737.28 seconds
Started Aug 19 06:02:09 PM PDT 24
Finished Aug 19 06:14:27 PM PDT 24
Peak memory 270872 kb
Host smart-c53552f4-d7ab-436e-a912-0692c290016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399458161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2399458161
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3246339685
Short name T270
Test name
Test status
Simulation time 144266654749 ps
CPU time 265.29 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:06:30 PM PDT 24
Peak memory 238624 kb
Host smart-68ca8ed3-f99f-407e-a25d-f5f95f0a59a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246339685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3246339685
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2793148441
Short name T609
Test name
Test status
Simulation time 3774025443 ps
CPU time 56.9 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:03:02 PM PDT 24
Peak memory 238524 kb
Host smart-b006abf4-e836-43cc-9989-d94ea9da863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793148441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2793148441
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2762923288
Short name T99
Test name
Test status
Simulation time 172560404375 ps
CPU time 254.26 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 266116 kb
Host smart-b968db0a-1a8f-4730-a112-046e711ddcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762923288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2762923288
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2703110234
Short name T722
Test name
Test status
Simulation time 751164435 ps
CPU time 5.61 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 232924 kb
Host smart-bc03699a-03c4-4074-8301-fc9e9142f54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703110234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2703110234
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.313064218
Short name T910
Test name
Test status
Simulation time 11456855042 ps
CPU time 25.21 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 239192 kb
Host smart-3a85aecd-6094-4b8b-807b-89e54682616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313064218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.313064218
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1646956141
Short name T8
Test name
Test status
Simulation time 17451969 ps
CPU time 1.02 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 216720 kb
Host smart-57427b7d-565d-4c30-992e-2c906a5292bc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646956141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1646956141
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3585387201
Short name T979
Test name
Test status
Simulation time 1042663946 ps
CPU time 9.96 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 232948 kb
Host smart-82ec3b24-27b1-4afe-aa6f-54adfc2fc079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585387201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3585387201
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3933281439
Short name T641
Test name
Test status
Simulation time 6948304017 ps
CPU time 20.35 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:31 PM PDT 24
Peak memory 232952 kb
Host smart-cfaa94e4-9d75-41bc-ba94-3f381c3bb5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933281439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3933281439
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2131612682
Short name T43
Test name
Test status
Simulation time 4632810860 ps
CPU time 15.32 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:19 PM PDT 24
Peak memory 220424 kb
Host smart-2ceb96df-2d1d-48ee-9e9e-eb458ac4a3b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131612682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2131612682
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2386055773
Short name T78
Test name
Test status
Simulation time 64193142 ps
CPU time 0.98 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 235620 kb
Host smart-725cd47f-187b-4104-855d-274dd4a961ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386055773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2386055773
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3427434761
Short name T231
Test name
Test status
Simulation time 1494595688213 ps
CPU time 770.17 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:15:02 PM PDT 24
Peak memory 283616 kb
Host smart-0c280cc8-1c30-4344-9fb6-85eb051105e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427434761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3427434761
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1107735452
Short name T685
Test name
Test status
Simulation time 3518870734 ps
CPU time 7.82 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 216568 kb
Host smart-e5f85fe8-20b8-4517-9b2f-9f771739abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107735452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1107735452
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3301840178
Short name T524
Test name
Test status
Simulation time 1108493061 ps
CPU time 2.24 seconds
Started Aug 19 06:02:05 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 207240 kb
Host smart-6d435c98-00ef-4193-be7e-fb6296283907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301840178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3301840178
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1378599482
Short name T439
Test name
Test status
Simulation time 15448774 ps
CPU time 0.83 seconds
Started Aug 19 06:02:07 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 206128 kb
Host smart-cbe9e876-e0f6-40eb-b91f-4701283dd5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378599482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1378599482
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1710646553
Short name T90
Test name
Test status
Simulation time 225433351 ps
CPU time 0.83 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 206092 kb
Host smart-58a8c689-db8a-4444-adbf-62f9b7612c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710646553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1710646553
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2707803993
Short name T414
Test name
Test status
Simulation time 135499026 ps
CPU time 2.62 seconds
Started Aug 19 06:02:04 PM PDT 24
Finished Aug 19 06:02:06 PM PDT 24
Peak memory 224716 kb
Host smart-9e5ea303-e550-47c0-ab00-809cf0cb933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707803993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2707803993
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2270071706
Short name T553
Test name
Test status
Simulation time 15668475 ps
CPU time 0.74 seconds
Started Aug 19 06:04:19 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 205880 kb
Host smart-bf1c3d79-1107-4bd2-9907-0d36f1aba32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270071706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2270071706
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4149169371
Short name T182
Test name
Test status
Simulation time 773959660 ps
CPU time 5.52 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 232912 kb
Host smart-039193db-3165-4d71-ac66-ebb0402a19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149169371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4149169371
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2788654924
Short name T178
Test name
Test status
Simulation time 145455874 ps
CPU time 0.75 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:04:18 PM PDT 24
Peak memory 206972 kb
Host smart-56b4dcb3-3a96-4726-b195-eb4a37703e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788654924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2788654924
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3603415876
Short name T1030
Test name
Test status
Simulation time 13128385 ps
CPU time 0.73 seconds
Started Aug 19 06:04:15 PM PDT 24
Finished Aug 19 06:04:16 PM PDT 24
Peak memory 215904 kb
Host smart-1017ff34-7c04-4430-98e0-932dc318edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603415876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3603415876
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3165661924
Short name T294
Test name
Test status
Simulation time 10079813838 ps
CPU time 157.16 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:06:56 PM PDT 24
Peak memory 253860 kb
Host smart-f846b9a8-f73f-4528-83d0-f8f0831f22ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165661924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3165661924
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4192539305
Short name T469
Test name
Test status
Simulation time 10356325683 ps
CPU time 128.03 seconds
Started Aug 19 06:04:16 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 252640 kb
Host smart-89233f7e-531d-4c68-9b67-e4b57df34aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192539305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4192539305
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.4021341596
Short name T289
Test name
Test status
Simulation time 39568677752 ps
CPU time 327.22 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:09:48 PM PDT 24
Peak memory 257276 kb
Host smart-6e605c07-c68f-4a07-ab10-45d2d5316020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021341596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.4021341596
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4200406786
Short name T768
Test name
Test status
Simulation time 134457184 ps
CPU time 2.18 seconds
Started Aug 19 06:04:15 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 222880 kb
Host smart-c70d2fed-c07f-4f0c-8a45-79101345d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200406786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4200406786
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1822557935
Short name T846
Test name
Test status
Simulation time 638375866 ps
CPU time 10.63 seconds
Started Aug 19 06:04:12 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 233120 kb
Host smart-b9ca9de0-242f-4534-b218-a7a7567d015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822557935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1822557935
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2066987920
Short name T233
Test name
Test status
Simulation time 155919114 ps
CPU time 3.22 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 232948 kb
Host smart-4e0863bf-441c-46ec-b2c5-5bb26e9ffc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066987920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2066987920
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.763335457
Short name T784
Test name
Test status
Simulation time 27907857124 ps
CPU time 9.78 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:30 PM PDT 24
Peak memory 224740 kb
Host smart-37e0d5da-c340-44ff-b84f-eaa7753f2fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763335457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.763335457
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2621485806
Short name T408
Test name
Test status
Simulation time 3349412833 ps
CPU time 10.2 seconds
Started Aug 19 06:04:14 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 223364 kb
Host smart-c17e81ba-358a-41f5-8215-4272c30120cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621485806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2621485806
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3201546863
Short name T170
Test name
Test status
Simulation time 11079209248 ps
CPU time 96.44 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:05:55 PM PDT 24
Peak memory 253572 kb
Host smart-464f0aaf-382c-4d35-bacd-168d5f26805f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201546863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3201546863
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4216561103
Short name T318
Test name
Test status
Simulation time 72903831 ps
CPU time 1.91 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:22 PM PDT 24
Peak memory 216884 kb
Host smart-dec45a54-398a-4bff-b20c-5e763d526c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216561103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4216561103
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1824878075
Short name T972
Test name
Test status
Simulation time 36270224 ps
CPU time 0.7 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:18 PM PDT 24
Peak memory 205772 kb
Host smart-40065884-1273-4c51-938d-0b5f244576d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824878075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1824878075
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.550537013
Short name T960
Test name
Test status
Simulation time 22902717 ps
CPU time 0.69 seconds
Started Aug 19 06:04:16 PM PDT 24
Finished Aug 19 06:04:17 PM PDT 24
Peak memory 205656 kb
Host smart-3881c2bf-07e8-45a4-a63b-6ee2efa1123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550537013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.550537013
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.337805260
Short name T327
Test name
Test status
Simulation time 286007082 ps
CPU time 1.01 seconds
Started Aug 19 06:04:14 PM PDT 24
Finished Aug 19 06:04:15 PM PDT 24
Peak memory 207160 kb
Host smart-23456763-aa75-45b6-932d-cda3b063342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337805260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.337805260
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3281580667
Short name T401
Test name
Test status
Simulation time 945622107 ps
CPU time 6.69 seconds
Started Aug 19 06:04:17 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 232904 kb
Host smart-72ad55a0-8992-401b-ac3d-86f430f39abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281580667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3281580667
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3258749522
Short name T418
Test name
Test status
Simulation time 28989981 ps
CPU time 0.7 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:25 PM PDT 24
Peak memory 204992 kb
Host smart-540bf8cf-ec15-4e60-b3e6-79a17d98a39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258749522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3258749522
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3423086842
Short name T638
Test name
Test status
Simulation time 1155483880 ps
CPU time 7.54 seconds
Started Aug 19 06:04:23 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 232924 kb
Host smart-3942ee3f-2997-418c-b02d-5b6d59130aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423086842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3423086842
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.599646795
Short name T66
Test name
Test status
Simulation time 20326991 ps
CPU time 0.77 seconds
Started Aug 19 06:04:18 PM PDT 24
Finished Aug 19 06:04:19 PM PDT 24
Peak memory 206628 kb
Host smart-b412878f-7845-4d90-90ce-6fb5f9ec01d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599646795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.599646795
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4218745310
Short name T248
Test name
Test status
Simulation time 2141269998 ps
CPU time 15.5 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:04:40 PM PDT 24
Peak memory 250328 kb
Host smart-62360dac-37b2-4e42-92ac-9f83f39b7b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218745310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4218745310
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3412419155
Short name T452
Test name
Test status
Simulation time 35133942917 ps
CPU time 95.37 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 249428 kb
Host smart-d153f73e-b964-4f72-98ab-7194bbb95a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412419155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3412419155
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1259275376
Short name T159
Test name
Test status
Simulation time 16124978036 ps
CPU time 113.89 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 241104 kb
Host smart-81a2ec5e-64a8-4515-9e8e-0ac375aaf54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259275376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1259275376
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4121838507
Short name T50
Test name
Test status
Simulation time 8966848229 ps
CPU time 19.98 seconds
Started Aug 19 06:04:28 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 224812 kb
Host smart-88482f68-48ba-4f1e-b668-781021984a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121838507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4121838507
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4111692019
Short name T593
Test name
Test status
Simulation time 911493916 ps
CPU time 6.91 seconds
Started Aug 19 06:04:28 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 232928 kb
Host smart-cdc911ef-fd41-40d0-ad1d-9da2603ac367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111692019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4111692019
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4864894
Short name T276
Test name
Test status
Simulation time 821001306 ps
CPU time 18.44 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:04:43 PM PDT 24
Peak memory 234988 kb
Host smart-2ca00bc0-77cf-4383-89ff-e84b9ce2c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4864894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4864894
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2743412443
Short name T620
Test name
Test status
Simulation time 125149635 ps
CPU time 3.06 seconds
Started Aug 19 06:04:26 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 224652 kb
Host smart-dc50112a-6621-4e5c-aae7-6430c93c2087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743412443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2743412443
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3918306597
Short name T204
Test name
Test status
Simulation time 670398714 ps
CPU time 4.37 seconds
Started Aug 19 06:04:28 PM PDT 24
Finished Aug 19 06:04:32 PM PDT 24
Peak memory 232944 kb
Host smart-a9ac80a2-aa81-467d-abdb-ab8c1d0849f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918306597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3918306597
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3581218759
Short name T128
Test name
Test status
Simulation time 574864524 ps
CPU time 7.94 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:04:33 PM PDT 24
Peak memory 221836 kb
Host smart-0c0b9a9a-64f4-4800-be3c-fa28d12713d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3581218759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3581218759
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2135299189
Short name T983
Test name
Test status
Simulation time 124468708771 ps
CPU time 288.18 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 265792 kb
Host smart-24160979-58c4-44a1-9cde-b85af3bbf504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135299189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2135299189
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.374195991
Short name T590
Test name
Test status
Simulation time 5665625892 ps
CPU time 25.28 seconds
Started Aug 19 06:04:19 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 216556 kb
Host smart-d59cbf59-66cb-4279-acb0-c9b5f5f731fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374195991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.374195991
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3938207768
Short name T348
Test name
Test status
Simulation time 110901834 ps
CPU time 0.71 seconds
Started Aug 19 06:04:20 PM PDT 24
Finished Aug 19 06:04:21 PM PDT 24
Peak memory 205740 kb
Host smart-c6312905-c37e-4fb4-ae81-712987696352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938207768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3938207768
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2073020180
Short name T955
Test name
Test status
Simulation time 30688029 ps
CPU time 0.7 seconds
Started Aug 19 06:04:27 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 205708 kb
Host smart-bc22ff9b-d70b-43eb-a84a-4e894f0cf0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073020180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2073020180
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.780242381
Short name T145
Test name
Test status
Simulation time 123786175 ps
CPU time 0.92 seconds
Started Aug 19 06:04:15 PM PDT 24
Finished Aug 19 06:04:16 PM PDT 24
Peak memory 207160 kb
Host smart-4551fe61-d2b5-4204-949c-0a8176f9f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780242381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.780242381
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3609093855
Short name T175
Test name
Test status
Simulation time 902559529 ps
CPU time 9.05 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:33 PM PDT 24
Peak memory 232896 kb
Host smart-14dd76a0-c56f-468f-b992-8d056862d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609093855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3609093855
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2686211016
Short name T344
Test name
Test status
Simulation time 22175274 ps
CPU time 0.72 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:36 PM PDT 24
Peak memory 205876 kb
Host smart-17e63356-b90f-4aa0-b157-fc462b87cafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686211016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2686211016
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3184092383
Short name T648
Test name
Test status
Simulation time 134648323 ps
CPU time 3.14 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 232888 kb
Host smart-8f94ab34-ade5-4be4-8502-4933c9b29753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184092383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3184092383
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.510288782
Short name T334
Test name
Test status
Simulation time 29841321 ps
CPU time 0.77 seconds
Started Aug 19 06:04:22 PM PDT 24
Finished Aug 19 06:04:23 PM PDT 24
Peak memory 206660 kb
Host smart-aa6302f8-3c2a-4749-a005-471e1d04c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510288782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.510288782
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2530920783
Short name T607
Test name
Test status
Simulation time 22902335892 ps
CPU time 108.47 seconds
Started Aug 19 06:04:26 PM PDT 24
Finished Aug 19 06:06:14 PM PDT 24
Peak memory 273172 kb
Host smart-805d7891-552d-4916-935f-89512324cd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530920783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2530920783
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.84075349
Short name T930
Test name
Test status
Simulation time 89467119790 ps
CPU time 611.9 seconds
Started Aug 19 06:04:21 PM PDT 24
Finished Aug 19 06:14:34 PM PDT 24
Peak memory 269572 kb
Host smart-31172c21-5232-4166-b1ce-ca57ef70df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84075349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.84075349
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2365560134
Short name T921
Test name
Test status
Simulation time 10421860573 ps
CPU time 58.32 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:05:34 PM PDT 24
Peak memory 233036 kb
Host smart-ac5538cf-155e-445a-99cf-102348dbc07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365560134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2365560134
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.319087541
Short name T729
Test name
Test status
Simulation time 423746090 ps
CPU time 3.89 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:29 PM PDT 24
Peak memory 224672 kb
Host smart-c0956deb-f71c-4230-98da-3cd566825307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319087541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.319087541
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1678626776
Short name T425
Test name
Test status
Simulation time 19829152268 ps
CPU time 34.43 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 257536 kb
Host smart-679331a2-ba8a-4b7e-a228-4673a722d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678626776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1678626776
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3927377466
Short name T494
Test name
Test status
Simulation time 203295718 ps
CPU time 4.53 seconds
Started Aug 19 06:04:26 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 232916 kb
Host smart-7fc71727-17a8-4f81-b0b0-c6aee5de0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927377466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3927377466
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.190452068
Short name T253
Test name
Test status
Simulation time 534452955 ps
CPU time 13.9 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 240508 kb
Host smart-ed42ca52-015e-4e78-9917-72fc16c41fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190452068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.190452068
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2011984466
Short name T916
Test name
Test status
Simulation time 1145682298 ps
CPU time 5.84 seconds
Started Aug 19 06:04:25 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 232908 kb
Host smart-35a68225-741d-4bb5-9744-b3fe6e4a6c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011984466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2011984466
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3839181826
Short name T570
Test name
Test status
Simulation time 698779627 ps
CPU time 6.24 seconds
Started Aug 19 06:04:27 PM PDT 24
Finished Aug 19 06:04:34 PM PDT 24
Peak memory 232920 kb
Host smart-f3a85e3f-83e4-4ec3-bb34-1d2e8ac6ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839181826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3839181826
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.353602179
Short name T835
Test name
Test status
Simulation time 499823876 ps
CPU time 3.89 seconds
Started Aug 19 06:04:26 PM PDT 24
Finished Aug 19 06:04:31 PM PDT 24
Peak memory 220508 kb
Host smart-5e629dfa-1126-4f61-baeb-810463b4bb6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=353602179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.353602179
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.630974147
Short name T717
Test name
Test status
Simulation time 3887248612 ps
CPU time 24.78 seconds
Started Aug 19 06:04:32 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 255136 kb
Host smart-4e3114b1-ba51-460e-b14f-f12c95c042cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630974147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.630974147
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3071501072
Short name T323
Test name
Test status
Simulation time 3795795705 ps
CPU time 12.63 seconds
Started Aug 19 06:04:23 PM PDT 24
Finished Aug 19 06:04:36 PM PDT 24
Peak memory 216548 kb
Host smart-e18b54b7-ef89-4f45-88a0-e0a5c3904313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071501072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3071501072
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1590086208
Short name T652
Test name
Test status
Simulation time 839523825 ps
CPU time 3.92 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:28 PM PDT 24
Peak memory 216616 kb
Host smart-93abe211-db7b-4540-8c3e-6f7e180e9f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590086208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1590086208
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2127027861
Short name T501
Test name
Test status
Simulation time 21825865 ps
CPU time 0.69 seconds
Started Aug 19 06:04:24 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 205676 kb
Host smart-ec1bb0b4-53db-4fa9-b4ed-dc783c4a27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127027861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2127027861
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.910180641
Short name T352
Test name
Test status
Simulation time 235364649 ps
CPU time 0.78 seconds
Started Aug 19 06:04:23 PM PDT 24
Finished Aug 19 06:04:24 PM PDT 24
Peak memory 206140 kb
Host smart-43810427-02d7-404e-9dcf-f50ee56770c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910180641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.910180641
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1782222050
Short name T666
Test name
Test status
Simulation time 4636211107 ps
CPU time 7.4 seconds
Started Aug 19 06:04:23 PM PDT 24
Finished Aug 19 06:04:30 PM PDT 24
Peak memory 224700 kb
Host smart-bdd5443a-cb4d-4342-8619-9bb8af046ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782222050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1782222050
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3943417175
Short name T394
Test name
Test status
Simulation time 26564431 ps
CPU time 0.73 seconds
Started Aug 19 06:04:36 PM PDT 24
Finished Aug 19 06:04:37 PM PDT 24
Peak memory 205552 kb
Host smart-4734b5ad-11a7-4973-b418-6245a3101a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943417175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3943417175
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3330888634
Short name T354
Test name
Test status
Simulation time 32610899 ps
CPU time 2.69 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 232476 kb
Host smart-927943b9-5566-4af3-b1fc-7028c2bd1fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330888634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3330888634
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2511451112
Short name T879
Test name
Test status
Simulation time 56039806 ps
CPU time 0.74 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 205604 kb
Host smart-6725269b-91d3-42aa-8627-4b2ac2e5c1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511451112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2511451112
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3374193760
Short name T207
Test name
Test status
Simulation time 2693394028 ps
CPU time 56.93 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 250408 kb
Host smart-1bef0f4b-17c2-47c5-a6a8-37128489c8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374193760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3374193760
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3338317437
Short name T567
Test name
Test status
Simulation time 43220388744 ps
CPU time 120.91 seconds
Started Aug 19 06:04:32 PM PDT 24
Finished Aug 19 06:06:33 PM PDT 24
Peak memory 255816 kb
Host smart-27193166-8740-4d1c-b44c-0f0b992225ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338317437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3338317437
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3192929371
Short name T190
Test name
Test status
Simulation time 3496493614 ps
CPU time 63.05 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:05:36 PM PDT 24
Peak memory 257616 kb
Host smart-166cda71-3b48-4b2f-a4b4-2c2ff94c5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192929371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3192929371
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2595066061
Short name T700
Test name
Test status
Simulation time 288953037 ps
CPU time 2.54 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 224716 kb
Host smart-b4b026cc-226a-474a-bc65-5c2ffbd630fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595066061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2595066061
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1767045149
Short name T851
Test name
Test status
Simulation time 97775120520 ps
CPU time 177.65 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 255876 kb
Host smart-95334dfb-8f15-487d-8685-427a1775f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767045149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1767045149
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3228920621
Short name T673
Test name
Test status
Simulation time 4101866919 ps
CPU time 39.19 seconds
Started Aug 19 06:04:36 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 232960 kb
Host smart-eef80cf8-1cfd-4afb-87c8-a9be6790dafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228920621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3228920621
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.449795800
Short name T759
Test name
Test status
Simulation time 8860998748 ps
CPU time 12.34 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 232932 kb
Host smart-5118ba17-e207-4681-864c-fa49bf710eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449795800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.449795800
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1026060813
Short name T432
Test name
Test status
Simulation time 182361062 ps
CPU time 2.34 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:37 PM PDT 24
Peak memory 224508 kb
Host smart-9c3a554e-b998-4ca4-be16-993615700f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026060813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1026060813
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1406861179
Short name T487
Test name
Test status
Simulation time 4875036946 ps
CPU time 11.77 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 222204 kb
Host smart-3098281d-c238-4aaa-8a00-abb072742b2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1406861179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1406861179
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2448287937
Short name T24
Test name
Test status
Simulation time 143038826 ps
CPU time 1.15 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 207044 kb
Host smart-fb601a2a-5f38-4a27-a537-b2f3a4fc31ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448287937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2448287937
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2795079676
Short name T455
Test name
Test status
Simulation time 5640094110 ps
CPU time 7.8 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:43 PM PDT 24
Peak memory 216556 kb
Host smart-a16de063-c145-4911-8597-37cd5801788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795079676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2795079676
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2447205360
Short name T359
Test name
Test status
Simulation time 3068838993 ps
CPU time 11.34 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 216580 kb
Host smart-ce419acb-0821-4ecb-8a07-adfb915b44e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447205360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2447205360
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3629180220
Short name T508
Test name
Test status
Simulation time 50701408 ps
CPU time 1.43 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:04:39 PM PDT 24
Peak memory 216396 kb
Host smart-f3221d1b-c04c-41eb-bcc3-810c6793d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629180220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3629180220
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3943909200
Short name T27
Test name
Test status
Simulation time 224619114 ps
CPU time 0.94 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:36 PM PDT 24
Peak memory 207152 kb
Host smart-ca526a36-9151-4437-93ef-53c8fac48a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943909200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3943909200
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1972026170
Short name T522
Test name
Test status
Simulation time 2135341133 ps
CPU time 4.97 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 232812 kb
Host smart-a0b1cb68-6da3-4fd5-a39e-a6d204f69cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972026170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1972026170
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3823569098
Short name T990
Test name
Test status
Simulation time 14564384 ps
CPU time 0.68 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 205916 kb
Host smart-4300e215-10e1-48ba-b698-3b00c54d7faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823569098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3823569098
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.28330196
Short name T911
Test name
Test status
Simulation time 30131683 ps
CPU time 2.7 seconds
Started Aug 19 06:04:36 PM PDT 24
Finished Aug 19 06:04:39 PM PDT 24
Peak memory 232472 kb
Host smart-16bf0023-3546-44f2-9601-13a6883b5958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28330196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.28330196
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2429828820
Short name T489
Test name
Test status
Simulation time 20889582 ps
CPU time 0.75 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:04:34 PM PDT 24
Peak memory 206908 kb
Host smart-777c40fa-28e7-4452-b77c-9389837767da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429828820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2429828820
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1796650630
Short name T931
Test name
Test status
Simulation time 84975997216 ps
CPU time 344.96 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:10:18 PM PDT 24
Peak memory 266544 kb
Host smart-957bee15-23ce-4e5e-b36c-7121de648362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796650630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1796650630
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3016744585
Short name T82
Test name
Test status
Simulation time 3160837246 ps
CPU time 73.38 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:05:56 PM PDT 24
Peak memory 254832 kb
Host smart-ae659141-ed02-44b0-b98b-6e174b320c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016744585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3016744585
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3213267669
Short name T296
Test name
Test status
Simulation time 316931225667 ps
CPU time 773.04 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:17:37 PM PDT 24
Peak memory 265812 kb
Host smart-2c5dd709-b26e-42c8-8821-00837e695104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213267669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3213267669
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1353219797
Short name T16
Test name
Test status
Simulation time 5211475023 ps
CPU time 22.93 seconds
Started Aug 19 06:04:35 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 224768 kb
Host smart-b8b93cd3-0f85-49a3-868e-2f9e6de7831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353219797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1353219797
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2338390226
Short name T581
Test name
Test status
Simulation time 101627992573 ps
CPU time 208.61 seconds
Started Aug 19 06:04:36 PM PDT 24
Finished Aug 19 06:08:05 PM PDT 24
Peak memory 250756 kb
Host smart-91272c9a-1ca2-4f5f-ad89-5a3c00498c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338390226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2338390226
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2667667930
Short name T1015
Test name
Test status
Simulation time 513397270 ps
CPU time 2.41 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 224672 kb
Host smart-2af65041-3277-4d4b-9dac-c3b04a616042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667667930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2667667930
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2073082124
Short name T882
Test name
Test status
Simulation time 3006706258 ps
CPU time 25.6 seconds
Started Aug 19 06:04:36 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 234020 kb
Host smart-e21fe9e5-feba-437d-9c65-bfcc2ccdbb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073082124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2073082124
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1627865418
Short name T1002
Test name
Test status
Simulation time 8655594535 ps
CPU time 20.74 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:55 PM PDT 24
Peak memory 232888 kb
Host smart-3c8cab32-7c35-49a3-b990-447926ae60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627865418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1627865418
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2701989395
Short name T244
Test name
Test status
Simulation time 3946818905 ps
CPU time 14.81 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:49 PM PDT 24
Peak memory 241012 kb
Host smart-e63e7bd5-a855-4681-9c6e-520e9c2448db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701989395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2701989395
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.111306743
Short name T762
Test name
Test status
Simulation time 133083565 ps
CPU time 3.53 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:04:37 PM PDT 24
Peak memory 219396 kb
Host smart-a80d48c9-e306-4f27-bc8d-f8aca2ed0dfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111306743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.111306743
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1155762895
Short name T719
Test name
Test status
Simulation time 10748660005 ps
CPU time 82.48 seconds
Started Aug 19 06:04:49 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 265788 kb
Host smart-b009b722-fa9f-4004-a403-9e43239a48ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155762895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1155762895
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2490793251
Short name T518
Test name
Test status
Simulation time 5370986476 ps
CPU time 15.75 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 220264 kb
Host smart-4f71ca23-a007-4f3f-b37d-88e36b49e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490793251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2490793251
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1507476764
Short name T876
Test name
Test status
Simulation time 1021460943 ps
CPU time 4.04 seconds
Started Aug 19 06:04:33 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 216516 kb
Host smart-48349018-4f5d-4942-908c-a57938d0b90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507476764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1507476764
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3257132471
Short name T790
Test name
Test status
Simulation time 17956681 ps
CPU time 1.05 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:04:38 PM PDT 24
Peak memory 216332 kb
Host smart-f5a360d7-0bec-4551-89e8-6d13df489b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257132471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3257132471
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3266621419
Short name T787
Test name
Test status
Simulation time 100658301 ps
CPU time 0.84 seconds
Started Aug 19 06:04:34 PM PDT 24
Finished Aug 19 06:04:35 PM PDT 24
Peak memory 206152 kb
Host smart-7a7ca23e-f52b-4eb0-88ca-60114ee3699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266621419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3266621419
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2979813987
Short name T260
Test name
Test status
Simulation time 146166301 ps
CPU time 3.42 seconds
Started Aug 19 06:04:37 PM PDT 24
Finished Aug 19 06:04:41 PM PDT 24
Peak memory 224668 kb
Host smart-c14d6cde-bfb6-4ea7-bb18-ad4caf0beb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979813987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2979813987
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3506799242
Short name T525
Test name
Test status
Simulation time 13660646 ps
CPU time 0.72 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:44 PM PDT 24
Peak memory 205560 kb
Host smart-4f9203e2-4020-414a-b353-3edc16913fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506799242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3506799242
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2347149474
Short name T252
Test name
Test status
Simulation time 4596271552 ps
CPU time 11.94 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 224796 kb
Host smart-ebac9127-0c0a-4f46-bed3-064524bc2217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347149474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2347149474
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1959061946
Short name T1018
Test name
Test status
Simulation time 58702585 ps
CPU time 0.77 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:04:43 PM PDT 24
Peak memory 206620 kb
Host smart-4f45f2ba-857c-41ce-9df8-5f7f0b9e1f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959061946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1959061946
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.117182147
Short name T594
Test name
Test status
Simulation time 27342914988 ps
CPU time 56.31 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:05:41 PM PDT 24
Peak memory 236612 kb
Host smart-fa3fe598-2155-4bdc-bb68-4c82bd1ce781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117182147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.117182147
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.804835273
Short name T621
Test name
Test status
Simulation time 9242425599 ps
CPU time 26.67 seconds
Started Aug 19 06:04:48 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 224768 kb
Host smart-d0fd31cf-18bc-43ce-b540-46526d8c4908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804835273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.804835273
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2842158654
Short name T920
Test name
Test status
Simulation time 714321311966 ps
CPU time 829.04 seconds
Started Aug 19 06:04:49 PM PDT 24
Finished Aug 19 06:18:38 PM PDT 24
Peak memory 252836 kb
Host smart-acf9fe02-3edd-4457-9455-56f4e0089274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842158654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2842158654
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3887998307
Short name T390
Test name
Test status
Simulation time 168047530 ps
CPU time 3.85 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 224712 kb
Host smart-e1f2cfc0-80c0-488c-aa95-c0b12c4a36f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887998307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3887998307
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3192135175
Short name T591
Test name
Test status
Simulation time 40349723633 ps
CPU time 157.84 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:07:20 PM PDT 24
Peak memory 256964 kb
Host smart-4d3dc3ac-a67d-427d-bbed-3f5736427922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192135175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3192135175
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.38867622
Short name T969
Test name
Test status
Simulation time 1017723202 ps
CPU time 9.59 seconds
Started Aug 19 06:04:47 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 232940 kb
Host smart-31b2991d-4ea1-4229-ba69-396f6bbaf757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38867622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.38867622
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1192372942
Short name T629
Test name
Test status
Simulation time 275906498 ps
CPU time 7.5 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 232868 kb
Host smart-9006c715-7c35-4516-84c0-a32f1e9939b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192372942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1192372942
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2757661962
Short name T478
Test name
Test status
Simulation time 94486419 ps
CPU time 3.24 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 232904 kb
Host smart-9d3417cf-6d39-4658-ac22-73110088308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757661962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2757661962
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2208382508
Short name T527
Test name
Test status
Simulation time 7942550656 ps
CPU time 26.41 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 240672 kb
Host smart-ff4ebe6d-575e-4965-844d-88b3b8a64293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208382508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2208382508
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2992695633
Short name T363
Test name
Test status
Simulation time 2262735632 ps
CPU time 23.79 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:05:06 PM PDT 24
Peak memory 219148 kb
Host smart-3142bb03-1c5f-4229-b731-c7906a12d5ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2992695633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2992695633
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1193864057
Short name T753
Test name
Test status
Simulation time 1909710899 ps
CPU time 7.28 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 216520 kb
Host smart-0edf1861-babd-40ad-a089-7bbf6b1a31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193864057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1193864057
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3152329324
Short name T736
Test name
Test status
Simulation time 3228811906 ps
CPU time 3.54 seconds
Started Aug 19 06:04:41 PM PDT 24
Finished Aug 19 06:04:44 PM PDT 24
Peak memory 216552 kb
Host smart-88da5cc7-d285-46db-9ed8-69510b86c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152329324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3152329324
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3056398683
Short name T769
Test name
Test status
Simulation time 26513163 ps
CPU time 1.59 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 216472 kb
Host smart-58eb95d1-8aa3-4fa5-99a5-b052bf0be8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056398683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3056398683
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.83643243
Short name T343
Test name
Test status
Simulation time 95351492 ps
CPU time 0.77 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 206108 kb
Host smart-07acc8a9-3092-48c6-874b-14bef9a7790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83643243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.83643243
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1111952066
Short name T734
Test name
Test status
Simulation time 752965309 ps
CPU time 5.26 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:51 PM PDT 24
Peak memory 224648 kb
Host smart-984f7a57-c672-45a0-9377-bf25b2039d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111952066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1111952066
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.377846744
Short name T744
Test name
Test status
Simulation time 34952136 ps
CPU time 0.69 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:04:43 PM PDT 24
Peak memory 204996 kb
Host smart-b7ce0658-6175-40ce-b2b8-5511454b63fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377846744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.377846744
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3822430727
Short name T375
Test name
Test status
Simulation time 91156570 ps
CPU time 2.17 seconds
Started Aug 19 06:04:42 PM PDT 24
Finished Aug 19 06:04:44 PM PDT 24
Peak memory 224088 kb
Host smart-b38a7e1b-4623-4a82-832e-a64df54bb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822430727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3822430727
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3117910286
Short name T179
Test name
Test status
Simulation time 18523808 ps
CPU time 0.76 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 206976 kb
Host smart-52cb274c-3a57-496e-a257-f1c0da002d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117910286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3117910286
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3493856757
Short name T971
Test name
Test status
Simulation time 1776006811 ps
CPU time 25.29 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:05:09 PM PDT 24
Peak memory 257488 kb
Host smart-2dc4f01f-4ddd-4e38-9827-50bb4cdcbda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493856757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3493856757
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3380270582
Short name T285
Test name
Test status
Simulation time 60737489221 ps
CPU time 287.65 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:09:32 PM PDT 24
Peak memory 263736 kb
Host smart-7a64e2d3-8d3e-4de9-a35d-f1692bb0edd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380270582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3380270582
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.821652893
Short name T694
Test name
Test status
Simulation time 23659878911 ps
CPU time 104.36 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 253564 kb
Host smart-293045e9-6323-4408-b45f-375469b408d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821652893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.821652893
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2473131666
Short name T770
Test name
Test status
Simulation time 1275798828 ps
CPU time 11.27 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 224684 kb
Host smart-3e96ff14-a31a-466b-9782-0d71b5beaab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473131666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2473131666
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2774422916
Short name T778
Test name
Test status
Simulation time 34094869517 ps
CPU time 139.05 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:07:04 PM PDT 24
Peak memory 249356 kb
Host smart-4a59beb0-d8c0-49b4-a0b4-b15872c6a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774422916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2774422916
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2529326357
Short name T221
Test name
Test status
Simulation time 5441027705 ps
CPU time 20.57 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:05:04 PM PDT 24
Peak memory 224792 kb
Host smart-5aef1be6-5b1a-4189-93f2-78a8c84bf1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529326357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2529326357
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.786327335
Short name T41
Test name
Test status
Simulation time 6976469724 ps
CPU time 12.31 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:04:55 PM PDT 24
Peak memory 224732 kb
Host smart-52aea077-b546-4a56-acb0-9901e1f555e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786327335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.786327335
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2755590081
Short name T821
Test name
Test status
Simulation time 308627255 ps
CPU time 3.42 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 232904 kb
Host smart-ae6f913d-6bd2-421b-9176-25537c4f2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755590081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2755590081
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3450204515
Short name T974
Test name
Test status
Simulation time 10412127740 ps
CPU time 11.04 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:04:55 PM PDT 24
Peak memory 232960 kb
Host smart-c39e539f-d083-49ee-b356-639bcb2e92fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450204515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3450204515
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2263212348
Short name T97
Test name
Test status
Simulation time 144437118 ps
CPU time 3.56 seconds
Started Aug 19 06:04:48 PM PDT 24
Finished Aug 19 06:04:51 PM PDT 24
Peak memory 218828 kb
Host smart-b3d4c4c6-703e-438a-b4ee-baea4ac30a55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2263212348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2263212348
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.352009918
Short name T183
Test name
Test status
Simulation time 9337988171 ps
CPU time 45.82 seconds
Started Aug 19 06:04:48 PM PDT 24
Finished Aug 19 06:05:33 PM PDT 24
Peak memory 250140 kb
Host smart-8dbaccda-8db9-46f3-8fa6-e469a82651b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352009918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.352009918
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3789459476
Short name T926
Test name
Test status
Simulation time 1793710635 ps
CPU time 3 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:04:48 PM PDT 24
Peak memory 216544 kb
Host smart-dd9526c3-dcc9-4535-846a-ac828ef1108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789459476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3789459476
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2728676321
Short name T671
Test name
Test status
Simulation time 3718984511 ps
CPU time 3.69 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 216592 kb
Host smart-a84480d6-12b7-4be9-8043-d9224d5cf0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728676321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2728676321
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2015405078
Short name T389
Test name
Test status
Simulation time 238497283 ps
CPU time 1.3 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 208288 kb
Host smart-db4aae12-a139-4164-b6a3-74395fcda6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015405078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2015405078
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1563951326
Short name T364
Test name
Test status
Simulation time 15450838 ps
CPU time 0.73 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:04:43 PM PDT 24
Peak memory 206132 kb
Host smart-a021aded-57c7-4bfa-b6de-ccbe2929cec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563951326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1563951326
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1021595331
Short name T201
Test name
Test status
Simulation time 20880741923 ps
CPU time 32.36 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 234512 kb
Host smart-fb20053c-d8d8-41c5-8c14-2057313ec57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021595331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1021595331
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1399081044
Short name T564
Test name
Test status
Simulation time 12991131 ps
CPU time 0.69 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 205516 kb
Host smart-9cfa010c-ddcb-42f3-92a2-1a751b526c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399081044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1399081044
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1699998570
Short name T897
Test name
Test status
Simulation time 4842187675 ps
CPU time 11.88 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 232972 kb
Host smart-530fc7d1-0a8f-46e1-9620-2c0161d27487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699998570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1699998570
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3172871509
Short name T149
Test name
Test status
Simulation time 64034343 ps
CPU time 0.83 seconds
Started Aug 19 06:04:44 PM PDT 24
Finished Aug 19 06:04:45 PM PDT 24
Peak memory 206976 kb
Host smart-96bb2328-4f8d-4711-92e8-a31120a62386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172871509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3172871509
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4230866845
Short name T46
Test name
Test status
Simulation time 27593696858 ps
CPU time 61.46 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:05:54 PM PDT 24
Peak memory 249380 kb
Host smart-d26b6390-b8f8-4689-95f7-c8eeb0bd8d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230866845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4230866845
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3160297813
Short name T60
Test name
Test status
Simulation time 23278507398 ps
CPU time 269 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:09:23 PM PDT 24
Peak memory 252644 kb
Host smart-db52f6d6-7178-4716-87ff-726d8bc6afa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160297813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3160297813
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2617413975
Short name T795
Test name
Test status
Simulation time 136846928526 ps
CPU time 624.32 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:15:17 PM PDT 24
Peak memory 256972 kb
Host smart-99268d89-af85-438e-9972-3c91a2f9e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617413975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2617413975
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.910151791
Short name T491
Test name
Test status
Simulation time 440534146 ps
CPU time 5.32 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 224728 kb
Host smart-94b0a7bb-02b3-4c25-b8fc-b99c4d26db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910151791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.910151791
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3923540962
Short name T633
Test name
Test status
Simulation time 6244425530 ps
CPU time 23.21 seconds
Started Aug 19 06:04:57 PM PDT 24
Finished Aug 19 06:05:21 PM PDT 24
Peak memory 233828 kb
Host smart-7a003097-d266-4487-910b-1b0b4adb8dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923540962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3923540962
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1178908118
Short name T653
Test name
Test status
Simulation time 8924882881 ps
CPU time 22.39 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:05:07 PM PDT 24
Peak memory 232960 kb
Host smart-4bb08274-3744-4bb6-b8f3-200d92af4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178908118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1178908118
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4194098329
Short name T676
Test name
Test status
Simulation time 1116088453 ps
CPU time 17.65 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:05:04 PM PDT 24
Peak memory 232872 kb
Host smart-628e6e8b-ced6-4e7c-b6eb-2d088cd5f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194098329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4194098329
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4039564538
Short name T284
Test name
Test status
Simulation time 6566279735 ps
CPU time 19.23 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 224744 kb
Host smart-16e6d6cc-2e0c-426f-93dc-21c689eb26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039564538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4039564538
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3245742420
Short name T219
Test name
Test status
Simulation time 707715991 ps
CPU time 3.3 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 224640 kb
Host smart-0d525501-9c28-4817-92a7-b06057d6377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245742420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3245742420
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1379395475
Short name T791
Test name
Test status
Simulation time 459705356 ps
CPU time 4.28 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 222628 kb
Host smart-8622c25e-0eb7-4be2-a226-040d8e64dcb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1379395475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1379395475
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2032145563
Short name T61
Test name
Test status
Simulation time 44670614284 ps
CPU time 234.35 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:08:45 PM PDT 24
Peak memory 250440 kb
Host smart-e3d2bced-3799-4aec-94f5-e1136299aa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032145563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2032145563
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2500597463
Short name T440
Test name
Test status
Simulation time 14108119832 ps
CPU time 32.8 seconds
Started Aug 19 06:04:43 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 216644 kb
Host smart-8070d181-ad69-4e63-9178-1f8be00fed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500597463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2500597463
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.704143480
Short name T340
Test name
Test status
Simulation time 66969336 ps
CPU time 0.68 seconds
Started Aug 19 06:04:45 PM PDT 24
Finished Aug 19 06:04:46 PM PDT 24
Peak memory 205744 kb
Host smart-61bee582-3490-4a1a-bae7-e2ff1e480f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704143480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.704143480
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.41801074
Short name T472
Test name
Test status
Simulation time 20849659 ps
CPU time 0.74 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 205672 kb
Host smart-208dc3ac-6155-423f-9b9a-64d055024290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41801074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.41801074
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.854117963
Short name T549
Test name
Test status
Simulation time 88602882 ps
CPU time 0.95 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:47 PM PDT 24
Peak memory 206152 kb
Host smart-0230e325-a874-426a-b3ea-b3a7779b7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854117963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.854117963
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2624920617
Short name T460
Test name
Test status
Simulation time 968245871 ps
CPU time 12.25 seconds
Started Aug 19 06:04:46 PM PDT 24
Finished Aug 19 06:04:59 PM PDT 24
Peak memory 240356 kb
Host smart-74a9f037-acc3-4751-bb35-a61d7b007c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624920617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2624920617
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2446863799
Short name T338
Test name
Test status
Simulation time 11916012 ps
CPU time 0.72 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 204932 kb
Host smart-8ecc019a-12fc-4abe-bedf-c610c9432d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446863799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2446863799
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3657886450
Short name T444
Test name
Test status
Simulation time 479345015 ps
CPU time 3.43 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 224748 kb
Host smart-8da7cf4c-b620-48d8-a861-1ede5905aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657886450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3657886450
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.674517628
Short name T822
Test name
Test status
Simulation time 15000644 ps
CPU time 0.78 seconds
Started Aug 19 06:04:55 PM PDT 24
Finished Aug 19 06:04:55 PM PDT 24
Peak memory 206628 kb
Host smart-7a6a5e88-b0c0-400a-b875-87c2aff8579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674517628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.674517628
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2892156182
Short name T766
Test name
Test status
Simulation time 9561776408 ps
CPU time 132.64 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 264136 kb
Host smart-b1570bf1-6cf3-4586-b703-e671007838e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892156182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2892156182
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2565883757
Short name T552
Test name
Test status
Simulation time 6136541733 ps
CPU time 78.5 seconds
Started Aug 19 06:04:57 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 250432 kb
Host smart-a7608c12-d537-48e3-87f0-48f8a50a4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565883757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2565883757
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2680265660
Short name T304
Test name
Test status
Simulation time 1110937212 ps
CPU time 20.91 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 232964 kb
Host smart-bbba140c-ecc1-4181-83eb-1ae5ef1f3036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680265660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2680265660
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.761865680
Short name T58
Test name
Test status
Simulation time 1737571912 ps
CPU time 22.77 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:05:14 PM PDT 24
Peak memory 239268 kb
Host smart-0d61ad4f-6187-4e66-a6c6-f81d2c2daffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761865680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.761865680
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2010993996
Short name T644
Test name
Test status
Simulation time 474977240 ps
CPU time 7.49 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 232920 kb
Host smart-164ea4c4-16b7-4df1-be38-9330cda7fb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010993996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2010993996
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3595695084
Short name T52
Test name
Test status
Simulation time 29778067826 ps
CPU time 35.2 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 248744 kb
Host smart-01defa10-0b47-46f2-879c-dddcabd5d14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595695084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3595695084
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2967661234
Short name T366
Test name
Test status
Simulation time 369048383 ps
CPU time 3.4 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 232916 kb
Host smart-16b4aaac-53bc-4179-8d90-cb971cde4f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967661234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2967661234
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1831607636
Short name T827
Test name
Test status
Simulation time 2913158227 ps
CPU time 10.97 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:05:04 PM PDT 24
Peak memory 232980 kb
Host smart-26b5257d-bcfd-46e1-afb5-fb967929a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831607636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1831607636
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2529613479
Short name T369
Test name
Test status
Simulation time 1872079889 ps
CPU time 15.15 seconds
Started Aug 19 06:04:57 PM PDT 24
Finished Aug 19 06:05:13 PM PDT 24
Peak memory 222048 kb
Host smart-f3fd64d0-ec01-4833-b706-f6fa41f7d352
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2529613479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2529613479
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2919938373
Short name T21
Test name
Test status
Simulation time 212531564 ps
CPU time 1.03 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 206740 kb
Host smart-428f71c2-f185-4bc6-b354-de21d7c0aab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919938373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2919938373
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.829009720
Short name T637
Test name
Test status
Simulation time 6117733261 ps
CPU time 38.74 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 216648 kb
Host smart-314f1f73-384a-4cf5-bef1-f2a5ff203b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829009720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.829009720
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3414138472
Short name T500
Test name
Test status
Simulation time 5061642225 ps
CPU time 12.11 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:05:05 PM PDT 24
Peak memory 216628 kb
Host smart-dededdf4-544b-437a-a95f-e291a599a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414138472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3414138472
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1469498640
Short name T657
Test name
Test status
Simulation time 323370356 ps
CPU time 4.59 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 216512 kb
Host smart-829be473-c5dc-44e4-aa20-ea849eeed21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469498640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1469498640
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2594838065
Short name T996
Test name
Test status
Simulation time 123246710 ps
CPU time 1.07 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 206512 kb
Host smart-2e811146-9e71-4f19-8013-463881d1044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594838065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2594838065
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.723370437
Short name T484
Test name
Test status
Simulation time 1088036995 ps
CPU time 6 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 224660 kb
Host smart-dca09b61-e639-4246-9451-955e3dd61bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723370437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.723370437
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4034260957
Short name T903
Test name
Test status
Simulation time 44086874 ps
CPU time 0.71 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 204980 kb
Host smart-577e836d-d6a2-4303-a8df-061914e0d899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034260957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4034260957
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1765196615
Short name T828
Test name
Test status
Simulation time 1146295464 ps
CPU time 3 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:04:53 PM PDT 24
Peak memory 224672 kb
Host smart-613ac5ee-c3b1-48f0-9c02-43d0773ac7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765196615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1765196615
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.817495907
Short name T938
Test name
Test status
Simulation time 58960416 ps
CPU time 0.81 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 206632 kb
Host smart-6a93b278-73f0-43e8-8ce4-dfdd7b9eea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817495907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.817495907
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2116342244
Short name T807
Test name
Test status
Simulation time 13707742 ps
CPU time 0.74 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 215900 kb
Host smart-1ec274ee-ab94-4e00-80a0-8e5d140247c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116342244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2116342244
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.77699644
Short name T801
Test name
Test status
Simulation time 21294495553 ps
CPU time 121.57 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 249948 kb
Host smart-80c1d57b-f289-4ab1-a34e-17a171015e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77699644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.77699644
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2579768352
Short name T1011
Test name
Test status
Simulation time 151315849125 ps
CPU time 408.61 seconds
Started Aug 19 06:04:57 PM PDT 24
Finished Aug 19 06:11:46 PM PDT 24
Peak memory 263240 kb
Host smart-48c82679-8c2c-46c8-a7c4-d34a300a9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579768352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2579768352
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1575350189
Short name T792
Test name
Test status
Simulation time 1765289611 ps
CPU time 7.18 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:04:59 PM PDT 24
Peak memory 224724 kb
Host smart-e4d04bf5-4a9d-4702-97eb-397a3c9966a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575350189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1575350189
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.100427337
Short name T212
Test name
Test status
Simulation time 37837089103 ps
CPU time 67.12 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:06:01 PM PDT 24
Peak memory 256000 kb
Host smart-a5e40a78-018e-4b40-b6ce-4ac8d335cf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100427337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.100427337
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.646002964
Short name T745
Test name
Test status
Simulation time 35753976 ps
CPU time 2.52 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 232580 kb
Host smart-0e739ceb-5607-4e19-b52e-6c2645f4e578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646002964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.646002964
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3234525673
Short name T977
Test name
Test status
Simulation time 3744282960 ps
CPU time 11.81 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 238212 kb
Host smart-3aa1e7d0-4ee4-4e08-95d4-7cd4934b177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234525673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3234525673
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2019635895
Short name T699
Test name
Test status
Simulation time 2445317903 ps
CPU time 7.52 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 224732 kb
Host smart-cc86e5e4-54b7-4bae-982e-16a864d740b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019635895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2019635895
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3251195873
Short name T647
Test name
Test status
Simulation time 3222291666 ps
CPU time 5.24 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 224704 kb
Host smart-5c36717a-b460-4710-9ad5-920bf4cd93f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251195873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3251195873
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.54796255
Short name T576
Test name
Test status
Simulation time 404304298 ps
CPU time 5.22 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:04:57 PM PDT 24
Peak memory 222536 kb
Host smart-2f6b7256-1f1b-4243-a4b7-3eb2630e4d69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=54796255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.54796255
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.184177463
Short name T298
Test name
Test status
Simulation time 30738531721 ps
CPU time 123.04 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 268116 kb
Host smart-85d349bf-ede6-4662-a14e-b3a92a87941d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184177463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.184177463
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1879413734
Short name T355
Test name
Test status
Simulation time 12099353 ps
CPU time 0.78 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:04:55 PM PDT 24
Peak memory 205772 kb
Host smart-693592b6-c4b9-440a-8621-146f124ac049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879413734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1879413734
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2767011871
Short name T380
Test name
Test status
Simulation time 7979949525 ps
CPU time 9.46 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 216556 kb
Host smart-2a8687b8-b274-4644-b7b5-d89dc71bdefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767011871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2767011871
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2691155452
Short name T548
Test name
Test status
Simulation time 11327134 ps
CPU time 0.67 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 205692 kb
Host smart-cee45511-1406-466f-b320-b53d37524a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691155452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2691155452
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1461826476
Short name T92
Test name
Test status
Simulation time 24818166 ps
CPU time 0.74 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 206144 kb
Host smart-86e6a83d-75d1-46db-be97-12b37addad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461826476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1461826476
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2253937353
Short name T234
Test name
Test status
Simulation time 166259270 ps
CPU time 3.64 seconds
Started Aug 19 06:04:56 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 232912 kb
Host smart-55302a18-542b-4955-9450-d6c40fe166c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253937353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2253937353
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.910532768
Short name T358
Test name
Test status
Simulation time 13777357 ps
CPU time 0.69 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:12 PM PDT 24
Peak memory 205896 kb
Host smart-f7e634f2-a32c-4eca-8e85-5c6856e59615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910532768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.910532768
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1279047285
Short name T514
Test name
Test status
Simulation time 989385239 ps
CPU time 11.63 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 232864 kb
Host smart-3421166d-98db-429c-b50b-ae96514e809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279047285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1279047285
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1667101929
Short name T775
Test name
Test status
Simulation time 13526094 ps
CPU time 0.8 seconds
Started Aug 19 06:02:07 PM PDT 24
Finished Aug 19 06:02:08 PM PDT 24
Peak memory 205604 kb
Host smart-33bc7146-1230-4321-845b-f45526bdbefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667101929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1667101929
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1450192208
Short name T239
Test name
Test status
Simulation time 1335079075 ps
CPU time 26.82 seconds
Started Aug 19 06:02:18 PM PDT 24
Finished Aug 19 06:02:45 PM PDT 24
Peak memory 249288 kb
Host smart-d34dd0e9-95ea-45c9-952e-d0bec1d845d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450192208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1450192208
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.7871210
Short name T313
Test name
Test status
Simulation time 12460651432 ps
CPU time 64.69 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:03:20 PM PDT 24
Peak memory 249456 kb
Host smart-855f44d1-2878-4db7-96ea-01555a94c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7871210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.7871210
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1889487860
Short name T860
Test name
Test status
Simulation time 4425181969 ps
CPU time 57.52 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:03:13 PM PDT 24
Peak memory 257148 kb
Host smart-27cb2079-51d0-4988-bc07-cafea2f99ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889487860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1889487860
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2448205114
Short name T470
Test name
Test status
Simulation time 1209145554 ps
CPU time 7.74 seconds
Started Aug 19 06:02:17 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 232924 kb
Host smart-f765df54-68cc-4250-854a-cda4b3907427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448205114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2448205114
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1332216786
Short name T565
Test name
Test status
Simulation time 182183808025 ps
CPU time 351.47 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 257524 kb
Host smart-5385746c-9cb3-4d3c-b734-2e073190fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332216786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1332216786
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1147641412
Short name T232
Test name
Test status
Simulation time 1278050718 ps
CPU time 5.63 seconds
Started Aug 19 06:02:12 PM PDT 24
Finished Aug 19 06:02:18 PM PDT 24
Peak memory 224716 kb
Host smart-3c7201da-f515-43db-a7ee-505236811305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147641412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1147641412
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2474937861
Short name T733
Test name
Test status
Simulation time 29388827851 ps
CPU time 82.15 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:03:36 PM PDT 24
Peak memory 233960 kb
Host smart-6a43d00c-fd59-44ab-a6f7-7086c9a98397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474937861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2474937861
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.979774803
Short name T995
Test name
Test status
Simulation time 32579856 ps
CPU time 1.13 seconds
Started Aug 19 06:02:08 PM PDT 24
Finished Aug 19 06:02:09 PM PDT 24
Peak memory 218072 kb
Host smart-156a5f45-c2e1-4cda-8278-d33b7b614a3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979774803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.979774803
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2442889709
Short name T224
Test name
Test status
Simulation time 572658933 ps
CPU time 3.09 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:14 PM PDT 24
Peak memory 224676 kb
Host smart-7ef081d5-4088-4999-9da9-b43c45c4f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442889709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2442889709
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1407976693
Short name T914
Test name
Test status
Simulation time 10181800136 ps
CPU time 12.99 seconds
Started Aug 19 06:02:12 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 224764 kb
Host smart-e6650b39-6c34-4cdc-8b93-af364647f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407976693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1407976693
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1066389198
Short name T662
Test name
Test status
Simulation time 8629316682 ps
CPU time 19.57 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 222144 kb
Host smart-b13115b8-bc87-435c-a535-1d7531d5852f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066389198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1066389198
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1867133484
Short name T295
Test name
Test status
Simulation time 232627220729 ps
CPU time 503.09 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:10:38 PM PDT 24
Peak memory 274004 kb
Host smart-84318adc-8126-41a7-9f10-e89476c23cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867133484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1867133484
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.147951377
Short name T397
Test name
Test status
Simulation time 896891951 ps
CPU time 14.42 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:28 PM PDT 24
Peak memory 216692 kb
Host smart-51d6ea81-7af1-4392-9042-dfde785aff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147951377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.147951377
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2896377823
Short name T829
Test name
Test status
Simulation time 215735294 ps
CPU time 1.1 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 207960 kb
Host smart-0df80e50-8d98-475e-955d-f1588eb72ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896377823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2896377823
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1415671073
Short name T1022
Test name
Test status
Simulation time 94344244 ps
CPU time 3.06 seconds
Started Aug 19 06:02:08 PM PDT 24
Finished Aug 19 06:02:11 PM PDT 24
Peak memory 216440 kb
Host smart-60851a2a-4640-45c8-8bc4-b96211032f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415671073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1415671073
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2985152719
Short name T981
Test name
Test status
Simulation time 36236852 ps
CPU time 0.78 seconds
Started Aug 19 06:02:06 PM PDT 24
Finished Aug 19 06:02:07 PM PDT 24
Peak memory 206120 kb
Host smart-879199ea-37da-43c3-8a96-57032e7b49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985152719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2985152719
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1008427327
Short name T454
Test name
Test status
Simulation time 826163272 ps
CPU time 7.43 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:21 PM PDT 24
Peak memory 224676 kb
Host smart-fc37e7fb-699d-4488-aba6-d4b203a19046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008427327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1008427327
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.551900920
Short name T64
Test name
Test status
Simulation time 16011740 ps
CPU time 0.72 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 204932 kb
Host smart-bb8d1a50-f02f-47dd-a426-18d350412356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551900920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.551900920
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2138027587
Short name T278
Test name
Test status
Simulation time 883287907 ps
CPU time 3.58 seconds
Started Aug 19 06:02:16 PM PDT 24
Finished Aug 19 06:02:20 PM PDT 24
Peak memory 224728 kb
Host smart-11441c67-327e-4ec5-a3c5-f3534af7bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138027587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2138027587
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1964139287
Short name T824
Test name
Test status
Simulation time 13541009 ps
CPU time 0.72 seconds
Started Aug 19 06:02:17 PM PDT 24
Finished Aug 19 06:02:18 PM PDT 24
Peak memory 205572 kb
Host smart-b3a14e4e-172b-4840-ae4b-12ee77d4a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964139287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1964139287
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2699359358
Short name T42
Test name
Test status
Simulation time 30671991069 ps
CPU time 226.46 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:06:00 PM PDT 24
Peak memory 253888 kb
Host smart-c5d2debc-135c-4ba7-91fc-ecda4ab7f6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699359358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2699359358
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3244404333
Short name T416
Test name
Test status
Simulation time 3851407473 ps
CPU time 51.67 seconds
Started Aug 19 06:02:15 PM PDT 24
Finished Aug 19 06:03:07 PM PDT 24
Peak memory 256180 kb
Host smart-dfa79c31-bff3-42d0-9f20-310a97bc9378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244404333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3244404333
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1707117184
Short name T84
Test name
Test status
Simulation time 15012095031 ps
CPU time 93.76 seconds
Started Aug 19 06:02:12 PM PDT 24
Finished Aug 19 06:03:46 PM PDT 24
Peak memory 257608 kb
Host smart-2b7660aa-698a-4a36-a083-b8e31d87d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707117184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1707117184
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.88888081
Short name T309
Test name
Test status
Simulation time 519619693 ps
CPU time 13.69 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 250540 kb
Host smart-58d9e8a0-3c8a-4465-86a7-34789cf576e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88888081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.88888081
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4050683157
Short name T727
Test name
Test status
Simulation time 10092579131 ps
CPU time 64.31 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:03:18 PM PDT 24
Peak memory 254644 kb
Host smart-3cf56dc9-670e-46d2-9269-932e1cf524a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050683157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4050683157
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2602673749
Short name T598
Test name
Test status
Simulation time 431763531 ps
CPU time 4.24 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:17 PM PDT 24
Peak memory 224888 kb
Host smart-8ae2da67-a855-4c81-82cd-c1fd88f55f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602673749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2602673749
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1330167240
Short name T834
Test name
Test status
Simulation time 639734391 ps
CPU time 11.62 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 224692 kb
Host smart-c782f99d-d7a5-4189-932d-57e93461c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330167240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1330167240
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3406367267
Short name T387
Test name
Test status
Simulation time 120976559 ps
CPU time 1.1 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:14 PM PDT 24
Peak memory 216804 kb
Host smart-022b1f17-9d2a-4221-9622-626fdd9d4f96
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406367267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3406367267
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.567167567
Short name T213
Test name
Test status
Simulation time 770907907 ps
CPU time 6.24 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:20 PM PDT 24
Peak memory 232852 kb
Host smart-1fb5bef6-3bd3-4aa3-b111-f1d4a48c25c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567167567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
567167567
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3522197220
Short name T836
Test name
Test status
Simulation time 6831413368 ps
CPU time 19.42 seconds
Started Aug 19 06:02:13 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 233120 kb
Host smart-d383223e-048b-48d5-aad3-9191aae2194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522197220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3522197220
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4063938550
Short name T689
Test name
Test status
Simulation time 1746286312 ps
CPU time 11.18 seconds
Started Aug 19 06:02:12 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 222420 kb
Host smart-b20cee10-0bde-450f-8c2b-196339e72317
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4063938550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4063938550
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1316778362
Short name T804
Test name
Test status
Simulation time 3573775284 ps
CPU time 34.27 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 235460 kb
Host smart-58b54f6b-a5af-43d7-8add-fc84320d757c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316778362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1316778362
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2688795070
Short name T997
Test name
Test status
Simulation time 6027258296 ps
CPU time 9.89 seconds
Started Aug 19 06:02:18 PM PDT 24
Finished Aug 19 06:02:28 PM PDT 24
Peak memory 216752 kb
Host smart-a1d12949-57a0-45ff-ac52-92e2b623c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688795070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2688795070
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1747357181
Short name T392
Test name
Test status
Simulation time 740973549 ps
CPU time 6.25 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:20 PM PDT 24
Peak memory 216484 kb
Host smart-1516b1d1-2186-4718-9ef8-c60cb3fbb1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747357181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1747357181
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.429753197
Short name T630
Test name
Test status
Simulation time 105922854 ps
CPU time 1.32 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 216536 kb
Host smart-2e30f6d2-ed80-4956-8734-834bba44539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429753197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.429753197
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1852023710
Short name T368
Test name
Test status
Simulation time 94368895 ps
CPU time 0.92 seconds
Started Aug 19 06:02:14 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 206552 kb
Host smart-002f077b-68b5-487c-8e4e-9800661af129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852023710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1852023710
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1582564332
Short name T750
Test name
Test status
Simulation time 1084879065 ps
CPU time 3.46 seconds
Started Aug 19 06:02:11 PM PDT 24
Finished Aug 19 06:02:15 PM PDT 24
Peak memory 224628 kb
Host smart-6064e0df-0af1-4f1c-971d-7ac337d02730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582564332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1582564332
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.922291846
Short name T967
Test name
Test status
Simulation time 11740305 ps
CPU time 0.7 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 205572 kb
Host smart-e9ca035f-9fb4-4981-8b93-67c22f7d90b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922291846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.922291846
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2896558295
Short name T476
Test name
Test status
Simulation time 4514993891 ps
CPU time 11.66 seconds
Started Aug 19 06:02:19 PM PDT 24
Finished Aug 19 06:02:31 PM PDT 24
Peak memory 224744 kb
Host smart-9c7f2407-ba5a-4be4-afa9-a02aa578171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896558295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2896558295
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2915110357
Short name T403
Test name
Test status
Simulation time 68286176 ps
CPU time 0.8 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 206628 kb
Host smart-ff22661e-006d-464c-96ac-19129cc7640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915110357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2915110357
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.924077008
Short name T222
Test name
Test status
Simulation time 266302640918 ps
CPU time 467.13 seconds
Started Aug 19 06:02:26 PM PDT 24
Finished Aug 19 06:10:13 PM PDT 24
Peak memory 249376 kb
Host smart-628c9252-5d42-489a-b1e3-1b8331902ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924077008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.924077008
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.193272409
Short name T723
Test name
Test status
Simulation time 210710093950 ps
CPU time 189.44 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 250244 kb
Host smart-6d9d3c14-eaab-46f1-9c0d-96b50999e3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193272409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.193272409
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2535619303
Short name T917
Test name
Test status
Simulation time 74167822848 ps
CPU time 179.79 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:05:22 PM PDT 24
Peak memory 255332 kb
Host smart-e92cc0bd-c725-449a-b1da-8125bfb309c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535619303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2535619303
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2252608422
Short name T1027
Test name
Test status
Simulation time 295144659 ps
CPU time 2.64 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 224660 kb
Host smart-5609b0b3-5b14-4696-b3bb-449cc1e82d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252608422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2252608422
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3192089243
Short name T826
Test name
Test status
Simulation time 19338810149 ps
CPU time 132.04 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:04:33 PM PDT 24
Peak memory 249716 kb
Host smart-49ab67aa-7045-47ec-8c03-8a25ad249d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192089243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3192089243
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2120321262
Short name T716
Test name
Test status
Simulation time 92409136 ps
CPU time 3.84 seconds
Started Aug 19 06:02:19 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 232932 kb
Host smart-e9c5fde3-f16c-4c13-9302-44c1d58868b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120321262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2120321262
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.996710942
Short name T542
Test name
Test status
Simulation time 3613082541 ps
CPU time 30.71 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:02:52 PM PDT 24
Peak memory 224784 kb
Host smart-e02e1556-a910-4dad-a3c4-c54ea97973eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996710942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.996710942
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1699873322
Short name T800
Test name
Test status
Simulation time 27871277 ps
CPU time 1.04 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 216748 kb
Host smart-5e4f8103-67de-489a-8346-c3a0c2f5de44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699873322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1699873322
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3264469748
Short name T915
Test name
Test status
Simulation time 380302359 ps
CPU time 2.4 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 224672 kb
Host smart-06ec0772-4278-45f7-a33f-4e17d849f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264469748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3264469748
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2707110620
Short name T245
Test name
Test status
Simulation time 239145787 ps
CPU time 2.67 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 224684 kb
Host smart-821a3703-c9f8-4fc8-a504-16f30c622b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707110620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2707110620
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2290814606
Short name T1031
Test name
Test status
Simulation time 516978069 ps
CPU time 4.35 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 220404 kb
Host smart-d71c5d28-3b1a-4755-b962-448b4468bbaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2290814606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2290814606
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.219275719
Short name T424
Test name
Test status
Simulation time 42979980191 ps
CPU time 44.01 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:03:04 PM PDT 24
Peak memory 216556 kb
Host smart-bf06947f-ee94-4186-a9e9-d8f4026fa5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219275719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.219275719
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.205067384
Short name T1007
Test name
Test status
Simulation time 674718349 ps
CPU time 2.33 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 216480 kb
Host smart-5b44a4ab-bd71-43e7-abe4-37d11a7a2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205067384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.205067384
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.253318904
Short name T742
Test name
Test status
Simulation time 208047075 ps
CPU time 5.82 seconds
Started Aug 19 06:02:18 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 216468 kb
Host smart-51d3fcb6-a5ad-42f7-9eca-ae6e42a4117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253318904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.253318904
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1447988470
Short name T422
Test name
Test status
Simulation time 77636818 ps
CPU time 0.73 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 206148 kb
Host smart-3fa5c617-da79-4d86-9962-1d8e2f66607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447988470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1447988470
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1265383012
Short name T15
Test name
Test status
Simulation time 401533614 ps
CPU time 3.36 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 232920 kb
Host smart-0f649684-dd09-4f04-98ff-335385e369b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265383012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1265383012
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.928386705
Short name T732
Test name
Test status
Simulation time 34952273 ps
CPU time 0.69 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 205916 kb
Host smart-c81147db-1bc4-4db6-96ab-0ec185a9c144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928386705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.928386705
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.977251869
Short name T465
Test name
Test status
Simulation time 115242151 ps
CPU time 2.47 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 232556 kb
Host smart-a6e98ba3-9ed1-49c9-ae29-5b7e900d2d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977251869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.977251869
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.991390859
Short name T73
Test name
Test status
Simulation time 18639462 ps
CPU time 0.76 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 206636 kb
Host smart-9b453662-0ae2-4217-b9f2-a30f8a3d28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991390859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.991390859
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4062541055
Short name T867
Test name
Test status
Simulation time 31887613389 ps
CPU time 260.64 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:06:43 PM PDT 24
Peak memory 255424 kb
Host smart-864ee93a-08b7-4c76-9642-e3e83a1dbd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062541055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4062541055
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1426304688
Short name T991
Test name
Test status
Simulation time 10648542983 ps
CPU time 10.75 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 217704 kb
Host smart-8a3c965c-bc3f-4c1f-97aa-519ece4ba4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426304688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1426304688
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3238807403
Short name T786
Test name
Test status
Simulation time 14045543433 ps
CPU time 36 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:03:07 PM PDT 24
Peak memory 236460 kb
Host smart-ffedf158-4aa8-47c0-9d46-721bbb15d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238807403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3238807403
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2320017316
Short name T1028
Test name
Test status
Simulation time 1777535782 ps
CPU time 15.92 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 232924 kb
Host smart-399eb894-02f8-4229-a03c-1339de8a0d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320017316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2320017316
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.364420983
Short name T242
Test name
Test status
Simulation time 6295675969 ps
CPU time 71.37 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:03:34 PM PDT 24
Peak memory 253316 kb
Host smart-a26bd8f3-02aa-4fc3-ad95-8e6edb47bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364420983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
364420983
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.83177852
Short name T528
Test name
Test status
Simulation time 2802513491 ps
CPU time 10.66 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 232972 kb
Host smart-c75f119a-1855-4b46-93e2-36eb6456de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83177852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.83177852
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1085565200
Short name T208
Test name
Test status
Simulation time 1025259536 ps
CPU time 9.64 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 233940 kb
Host smart-4e87dd74-21ac-4670-aa47-5fefb7845586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085565200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1085565200
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.428884868
Short name T404
Test name
Test status
Simulation time 40565165 ps
CPU time 1.11 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:23 PM PDT 24
Peak memory 216772 kb
Host smart-2073eb75-6037-4040-bf82-04ef798c8246
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428884868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.428884868
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3682318321
Short name T875
Test name
Test status
Simulation time 13246072142 ps
CPU time 10.43 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:33 PM PDT 24
Peak memory 232932 kb
Host smart-408207df-5a59-41e0-9da2-71cf88f4e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682318321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3682318321
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.730593556
Short name T374
Test name
Test status
Simulation time 499068710 ps
CPU time 5.53 seconds
Started Aug 19 06:02:20 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 232952 kb
Host smart-e2515fd2-9dfa-4ff4-a855-ec265cba95de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730593556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.730593556
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2613537249
Short name T658
Test name
Test status
Simulation time 617982498 ps
CPU time 3.45 seconds
Started Aug 19 06:02:22 PM PDT 24
Finished Aug 19 06:02:25 PM PDT 24
Peak memory 220612 kb
Host smart-d1b73328-688b-4816-bf12-08e36b0b136c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2613537249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2613537249
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4133767428
Short name T153
Test name
Test status
Simulation time 58038547658 ps
CPU time 391.15 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 285916 kb
Host smart-a2503824-8937-40dd-87c7-da56c2854cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133767428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4133767428
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3125220852
Short name T1006
Test name
Test status
Simulation time 1302227997 ps
CPU time 3.37 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:27 PM PDT 24
Peak memory 216524 kb
Host smart-70b29c22-9d16-46cb-bdb1-70b608f25fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125220852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3125220852
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.229257592
Short name T502
Test name
Test status
Simulation time 1850725030 ps
CPU time 4.59 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:02:26 PM PDT 24
Peak memory 216516 kb
Host smart-834defdb-2138-4353-8c87-f401409b6429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229257592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.229257592
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1800083793
Short name T861
Test name
Test status
Simulation time 15667829 ps
CPU time 0.7 seconds
Started Aug 19 06:02:23 PM PDT 24
Finished Aug 19 06:02:24 PM PDT 24
Peak memory 205676 kb
Host smart-5dc86968-9ca3-46b8-bedc-6a3d543c6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800083793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1800083793
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.331914926
Short name T376
Test name
Test status
Simulation time 89142693 ps
CPU time 0.96 seconds
Started Aug 19 06:02:21 PM PDT 24
Finished Aug 19 06:02:22 PM PDT 24
Peak memory 207140 kb
Host smart-5781c62a-116a-4453-961b-e66e21fdef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331914926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.331914926
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1158577016
Short name T816
Test name
Test status
Simulation time 166785979 ps
CPU time 4.76 seconds
Started Aug 19 06:02:24 PM PDT 24
Finished Aug 19 06:02:28 PM PDT 24
Peak memory 232900 kb
Host smart-94ca6b45-0cdb-4684-ada6-a0f007dc715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158577016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1158577016
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.638349030
Short name T442
Test name
Test status
Simulation time 13900091 ps
CPU time 0.72 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 205852 kb
Host smart-876edda5-56c6-4abc-ad7e-5360a65d7cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638349030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.638349030
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2024273112
Short name T718
Test name
Test status
Simulation time 96232267 ps
CPU time 3.08 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 224744 kb
Host smart-3a1d10cb-11e8-4831-a871-575adc96ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024273112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2024273112
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3260125855
Short name T1014
Test name
Test status
Simulation time 15661444 ps
CPU time 0.76 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 205608 kb
Host smart-4e947fb6-8c0a-4df7-b256-4a9cadaa504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260125855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3260125855
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3424725251
Short name T878
Test name
Test status
Simulation time 1101269914 ps
CPU time 21.93 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:55 PM PDT 24
Peak memory 249620 kb
Host smart-472f49d0-f15b-400d-a3cb-6542c5353c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424725251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3424725251
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1789022690
Short name T273
Test name
Test status
Simulation time 76452583045 ps
CPU time 384.24 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:08:58 PM PDT 24
Peak memory 257608 kb
Host smart-40ddbd64-7db7-44cb-9294-7ea7b776c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789022690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1789022690
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.667363622
Short name T805
Test name
Test status
Simulation time 311588008737 ps
CPU time 159.76 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 252332 kb
Host smart-016cdf18-dae5-4c10-923f-cd4158b12d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667363622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
667363622
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.830928368
Short name T858
Test name
Test status
Simulation time 330274957 ps
CPU time 5.56 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:37 PM PDT 24
Peak memory 232848 kb
Host smart-86a930b1-581e-4f3b-89b2-6db15b663f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830928368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.830928368
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3748712707
Short name T840
Test name
Test status
Simulation time 83581934450 ps
CPU time 247.98 seconds
Started Aug 19 06:02:35 PM PDT 24
Finished Aug 19 06:06:43 PM PDT 24
Peak memory 253756 kb
Host smart-a5d7580a-4569-46e8-9143-3ceb5b85bf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748712707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3748712707
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.476075158
Short name T557
Test name
Test status
Simulation time 120387535 ps
CPU time 3.08 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:33 PM PDT 24
Peak memory 224488 kb
Host smart-5abc9bea-e729-4400-ac32-4d0ee4c8051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476075158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.476075158
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1649831515
Short name T622
Test name
Test status
Simulation time 982767908 ps
CPU time 12.79 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:46 PM PDT 24
Peak memory 224676 kb
Host smart-98aacde4-6b74-4bae-a093-1d68031d1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649831515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1649831515
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.903859158
Short name T342
Test name
Test status
Simulation time 78243530 ps
CPU time 1.03 seconds
Started Aug 19 06:02:33 PM PDT 24
Finished Aug 19 06:02:34 PM PDT 24
Peak memory 218008 kb
Host smart-957c7a52-e6f2-4ad1-803c-7f4672dc1c2a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903859158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.903859158
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.634239786
Short name T941
Test name
Test status
Simulation time 41483136706 ps
CPU time 16.73 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:48 PM PDT 24
Peak memory 232968 kb
Host smart-5ba68bf4-f9bb-4754-99f1-2ce007f8cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634239786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
634239786
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1801521113
Short name T150
Test name
Test status
Simulation time 2115336722 ps
CPU time 4.83 seconds
Started Aug 19 06:02:34 PM PDT 24
Finished Aug 19 06:02:39 PM PDT 24
Peak memory 232948 kb
Host smart-805b59e0-b911-42a3-b32b-cb620abae661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801521113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1801521113
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.209937325
Short name T715
Test name
Test status
Simulation time 1701491459 ps
CPU time 7.32 seconds
Started Aug 19 06:02:32 PM PDT 24
Finished Aug 19 06:02:39 PM PDT 24
Peak memory 222100 kb
Host smart-65880fd6-5edf-4eb8-b964-858fe1657215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=209937325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.209937325
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.719886448
Short name T562
Test name
Test status
Simulation time 1086041596 ps
CPU time 11.75 seconds
Started Aug 19 06:02:31 PM PDT 24
Finished Aug 19 06:02:43 PM PDT 24
Peak memory 216560 kb
Host smart-bf6a98e5-0645-4a7c-b7ef-cb9a44f01730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719886448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.719886448
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.874411636
Short name T681
Test name
Test status
Simulation time 316976966 ps
CPU time 1.93 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:32 PM PDT 24
Peak memory 208136 kb
Host smart-9e3f0fe4-02a5-4dc0-9c57-a399bc0a14a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874411636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.874411636
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2846258632
Short name T473
Test name
Test status
Simulation time 740957654 ps
CPU time 10.33 seconds
Started Aug 19 06:02:30 PM PDT 24
Finished Aug 19 06:02:40 PM PDT 24
Peak memory 216524 kb
Host smart-dbe40759-d361-45eb-b60d-1b7dcab71fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846258632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2846258632
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3239750489
Short name T339
Test name
Test status
Simulation time 19350892 ps
CPU time 0.72 seconds
Started Aug 19 06:02:29 PM PDT 24
Finished Aug 19 06:02:30 PM PDT 24
Peak memory 206152 kb
Host smart-3032007c-5518-4207-964e-faaa0663a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239750489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3239750489
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1397672077
Short name T147
Test name
Test status
Simulation time 26209013926 ps
CPU time 22.39 seconds
Started Aug 19 06:02:40 PM PDT 24
Finished Aug 19 06:03:03 PM PDT 24
Peak memory 240320 kb
Host smart-6a307112-ab35-4f29-90df-604f64cd147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397672077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1397672077
Directory /workspace/9.spi_device_upload/latest
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