Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2834164	1			T1	1		T2	6257		T3	1
all_values[1]	2834164	1			T1	1		T2	6257		T3	1
all_values[2]	2834164	1			T1	1		T2	6257		T3	1
all_values[3]	2834164	1			T1	1		T2	6257		T3	1
all_values[4]	2834164	1			T1	1		T2	6257		T3	1
all_values[5]	2834164	1			T1	1		T2	6257		T3	1
all_values[6]	2834164	1			T1	1		T2	6257		T3	1
all_values[7]	2834164	1			T1	1		T2	6257		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283854

1

T1

8

T2

50056

T3

8

auto[1]

1389458

1

T25

78

T35

145

T36

14619

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22644946

1

T1

8

T2

49991

T3

8

auto[1]

28366

1

T2

65

T25

63

T55

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2569456	1			T1	1		T2	6213		T3	1
all_values[0]	auto[0]	auto[1]	12684	1			T2	44		T25	4		T53	51
all_values[0]	auto[1]	auto[0]	250922	1			T25	3		T35	9		T36	2409
all_values[0]	auto[1]	auto[1]	1102	1			T25	6		T35	8		T36	22
all_values[1]	auto[0]	auto[0]	2715686	1			T1	1		T2	6236		T3	1
all_values[1]	auto[0]	auto[1]	8607	1			T2	21		T25	1		T53	51
all_values[1]	auto[1]	auto[0]	109319	1			T25	6		T35	16		T36	2411
all_values[1]	auto[1]	auto[1]	552	1			T25	7		T35	7		T36	25
all_values[2]	auto[0]	auto[0]	2619869	1			T1	1		T2	6257		T3	1
all_values[2]	auto[0]	auto[1]	2998	1			T25	5		T124	2		T35	2
all_values[2]	auto[1]	auto[0]	210897	1			T25	3		T35	14		T36	2430
all_values[2]	auto[1]	auto[1]	400	1			T25	3		T35	9		T36	2
all_values[3]	auto[0]	auto[0]	2792207	1			T1	1		T2	6257		T3	1
all_values[3]	auto[0]	auto[1]	213	1			T25	5		T35	3		T36	2
all_values[3]	auto[1]	auto[0]	41543	1			T25	3		T35	4		T36	2427
all_values[3]	auto[1]	auto[1]	201	1			T25	4		T35	11		T36	7
all_values[4]	auto[0]	auto[0]	2576559	1			T1	1		T2	6257		T3	1
all_values[4]	auto[0]	auto[1]	210	1			T25	5		T55	2		T35	7
all_values[4]	auto[1]	auto[0]	257172	1			T25	5		T35	11		T36	6
all_values[4]	auto[1]	auto[1]	223	1			T25	2		T35	7		T36	3
all_values[5]	auto[0]	auto[0]	2734927	1			T1	1		T2	6257		T3	1
all_values[5]	auto[0]	auto[1]	181	1			T25	2		T35	5		T37	1
all_values[5]	auto[1]	auto[0]	98873	1			T25	7		T35	16		T36	2432
all_values[5]	auto[1]	auto[1]	183	1			T25	3		T35	5		T36	6
all_values[6]	auto[0]	auto[0]	2669949	1			T1	1		T2	6257		T3	1
all_values[6]	auto[0]	auto[1]	212	1			T25	4		T35	9		T36	6
all_values[6]	auto[1]	auto[0]	163806	1			T25	9		T35	9		T36	7
all_values[6]	auto[1]	auto[1]	197	1			T25	4		T35	3		T36	1
all_values[7]	auto[0]	auto[0]	2579901	1			T1	1		T2	6257		T3	1
all_values[7]	auto[0]	auto[1]	195	1			T25	3		T35	7		T36	4
all_values[7]	auto[1]	auto[0]	253860	1			T25	8		T35	11		T36	2427
all_values[7]	auto[1]	auto[1]	208	1			T25	5		T35	5		T36	4