Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36434	1			T2	16		T8	12		T15	4
auto[SpiFlashAddrCfg]	7860	1			T2	3		T18	2		T51	6
auto[SpiFlashAddr3b]	9355	1			T2	6		T16	6		T18	4
auto[SpiFlashAddr4b]	7596	1			T2	4		T16	2		T18	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34220

1

T2

17

T8

12

T15

4

auto[1]

27025

1

T2

12

T23

2

T56

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31435

1

T2

21

T8

12

T15

4

auto[1]

29810

1

T2

8

T16

2

T18

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41284	1			T2	22		T8	12		T15	4
values[1]	1080	1			T62	2		T52	6		T53	1
values[2]	1568	1			T59	4		T52	4		T53	6
values[3]	1581	1			T51	6		T58	2		T56	2
values[4]	1495	1			T56	6		T64	4		T52	6
values[5]	1509	1			T16	4		T20	2		T56	4
values[6]	1472	1			T56	2		T57	2		T52	2
values[7]	1408	1			T2	1		T56	2		T104	2
values[8]	9848	1			T2	6		T18	8		T51	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27671

1

T8

12

T15

4

T16

10

auto[1]

33574

1

T2

29

T54

4

T55

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57747

1

T2

25

T8

12

T15

4

write

3498

1

T2

4

T20

4

T59

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19488

1

T2

10

T8

12

T15

4

valids[0x1]

41757

1

T2

19

T16

4

T18

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1657	1			T23	2		T57	2		T52	12
internal_process_ops[0x5a]	1592	1			T2	2		T57	2		T59	2
internal_process_ops[0x05]	22073	1			T2	9		T20	46		T105	2
internal_process_ops[0x35]	1602	1			T2	2		T18	4		T58	2
internal_process_ops[0x15]	1618	1			T16	2		T57	2		T104	2
internal_process_ops[0x03]	970	1			T58	2		T57	4		T54	1
internal_process_ops[0x0b]	955	1			T18	4		T52	4		T75	2
internal_process_ops[0x3b]	980	1			T2	1		T51	6		T57	2
internal_process_ops[0x6b]	1017	1			T16	4		T51	4		T56	2
internal_process_ops[0xbb]	991	1			T18	2		T54	3		T61	2
internal_process_ops[0xeb]	1032	1			T18	2		T56	2		T57	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59437

1

T2

29

T8

12

T15

4

auto[1]

1808

1

T52

17

T66

6

T53

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58788

1

T2

25

T8

12

T15

4

auto[1]

2457

1

T2

4

T20

4

T60

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8894

1

T8

12

T15

4

T16

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6140

1

T23

2

T56

2

T66

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1888

1

T18

2

T51

6

T58

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1648

1

T56

10

T64

4

T66

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2260

1

T16

6

T18

4

T51

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1970

1

T56

2

T64

4

T63

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1758

1

T16

2

T18

2

T20

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1573

1

T56

6

T64

2

T66

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T20

4

T59

2

T60

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T69

1

T93

1

T190

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

81

1

T103

1

T69

1

T123

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T66

2

T68

4

T71

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T69

1

T123

2

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T72

1

T191

8

T192

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T123

2

T38

3

T191

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T66

4

T71

4

T69

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

118

1

T100

2

T193

6

T103

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T124

1

T123

3

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

76

1

T93

3

T192

1

T194

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

102

1

T63

2

T68

6

T38

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

88

1

T65

2

T100

2

T124

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T38

1

T70

3

T195

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T63

1

T69

1

T123

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

103

1

T124

1

T71

2

T69

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12005

1

T2

7

T52

413

T53

45

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8527

1

T2

9

T52

303

T53

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1738

1

T2

3

T55

1

T52

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1685

1

T52

15

T53

8

T49

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2195

1

T2

3

T54

1

T55

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2076

1

T2

2

T52

23

T53

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1686

1

T2

1

T54

3

T52

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1704

1

T52

18

T53

6

T49

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

115

1

T52

1

T98

1

T99

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

114

1

T52

1

T53

2

T49

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

117

1

T52

1

T98

1

T101

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

141

1

T52

7

T53

1

T98

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

122

1

T52

1

T49

2

T99

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

152

1

T52

1

T101

1

T109

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

109

1

T52

2

T98

3

T101

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

132

1

T52

3

T98

3

T101

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T2

1

T52

1

T101

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T196

2

T112

1

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

116

1

T52

4

T53

1

T49

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

140

1

T52

5

T53

1

T49

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

128

1

T2

2

T52

1

T53

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

135

1

T101

1

T197

2

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

121

1

T2

1

T52

1

T53

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

112

1

T49

1

T109

2

T121

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3506	1			T8	12		T15	4		T16	2
auto[0]	values[0]	valids[0x1]	14317	1			T16	4		T18	4		T20	50
auto[0]	values[1]	valids[0x1]	455	1			T62	2		T63	3		T198	2
auto[0]	values[2]	valids[0x0]	503	1			T59	4		T78	2		T199	2
auto[0]	values[2]	valids[0x1]	282	1			T124	2		T103	1		T69	2
auto[0]	values[3]	valids[0x0]	505	1			T51	6		T58	2		T61	2
auto[0]	values[3]	valids[0x1]	282	1			T56	2		T63	3		T124	1
auto[0]	values[4]	valids[0x0]	501	1			T56	6		T64	4		T65	4
auto[0]	values[4]	valids[0x1]	253	1			T48	4		T103	2		T69	3
auto[0]	values[5]	valids[0x0]	493	1			T16	4		T20	2		T56	4
auto[0]	values[5]	valids[0x1]	264	1			T60	2		T66	2		T48	2
auto[0]	values[6]	valids[0x0]	473	1			T56	2		T57	2		T79	2
auto[0]	values[6]	valids[0x1]	269	1			T68	8		T103	1		T69	8
auto[0]	values[7]	valids[0x0]	425	1			T104	2		T48	10		T200	4
auto[0]	values[7]	valids[0x1]	232	1			T56	2		T103	1		T69	8
auto[0]	values[8]	valids[0x0]	3107	1			T18	4		T51	4		T56	4
auto[0]	values[8]	valids[0x1]	1804	1			T18	4		T58	4		T57	6
auto[1]	values[0]	valids[0x0]	4441	1			T2	7		T52	41		T53	27
auto[1]	values[0]	valids[0x1]	19020	1			T2	15		T52	731		T53	63
auto[1]	values[1]	valids[0x1]	625	1			T52	6		T53	1		T49	5
auto[1]	values[2]	valids[0x0]	440	1			T52	3		T53	5		T98	6
auto[1]	values[2]	valids[0x1]	343	1			T52	1		T53	1		T49	1
auto[1]	values[3]	valids[0x0]	459	1			T52	4		T53	2		T49	7
auto[1]	values[3]	valids[0x1]	335	1			T52	2		T53	5		T98	4
auto[1]	values[4]	valids[0x0]	446	1			T52	3		T53	4		T49	3
auto[1]	values[4]	valids[0x1]	295	1			T52	3		T49	2		T99	4
auto[1]	values[5]	valids[0x0]	411	1			T52	2		T53	4		T49	2
auto[1]	values[5]	valids[0x1]	341	1			T52	1		T49	1		T99	7
auto[1]	values[6]	valids[0x0]	421	1			T75	1		T49	6		T98	1
auto[1]	values[6]	valids[0x1]	309	1			T52	2		T49	2		T98	4
auto[1]	values[7]	valids[0x0]	429	1			T52	7		T53	3		T49	3
auto[1]	values[7]	valids[0x1]	322	1			T2	1		T52	2		T53	2
auto[1]	values[8]	valids[0x0]	2928	1			T2	3		T54	3		T55	2
auto[1]	values[8]	valids[0x1]	2009	1			T2	3		T54	1		T52	17