Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3682069

1

T2

2981

T7

1

T8

36

auto[1]

32435

1

T2

9

T20

46

T60

12

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199100

1

T2

14

T7

1

T8

36

auto[1]

2515404

1

T2

2976

T18

1024

T20

46

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	723762	1			T2	1		T7	1		T8	11
auto[524288:1048575]	424263	1			T2	1		T15	1		T18	497
auto[1048576:1572863]	462231	1			T8	5		T18	927		T51	56
auto[1572864:2097151]	472653	1			T2	5		T18	231		T51	8
auto[2097152:2621439]	395253	1			T2	2654		T8	5		T18	268
auto[2621440:3145727]	417043	1			T2	315		T8	1		T18	109
auto[3145728:3670015]	437331	1			T18	55		T51	385		T106	280
auto[3670016:4194303]	381968	1			T2	14		T8	14		T18	96

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2550382

1

T2

2990

T7

1

T8

16

auto[1]

1164122

1

T8

20

T9

56

T15

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3220429

1

T2

22

T7

1

T8

6

auto[1]

494075

1

T2

2968

T8

30

T15

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	237434	1			T2	1		T7	1		T8	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	412134	1			T18	509		T20	4		T105	768
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123458	1			T2	1		T18	238		T51	238
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	223239	1			T18	259		T57	1		T52	647
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	167313	1			T18	927		T51	56		T106	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	236728	1			T105	1		T52	1529		T53	2577
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	174835	1			T2	3		T18	231		T51	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	231291	1			T2	1		T105	57		T52	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	124518	1			T2	1		T18	12		T51	564
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	221711	1			T18	256		T105	718		T52	2180
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	138392	1			T8	1		T18	109		T146	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	206120	1			T52	1		T53	2		T49	2204
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	113774	1			T18	55		T51	385		T57	932
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	269688	1			T52	261		T98	260		T99	565
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	101170	1			T2	3		T18	96		T105	47
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	213917	1			T2	3		T57	769		T52	402
auto[0]	auto[1]	auto[0:524287]	auto[0]	1362	1			T8	6		T15	1		T106	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	66328	1			T53	641		T63	2		T101	3398
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2525	1			T15	1		T106	1		T53	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71499	1			T121	512		T112	477		T36	2043
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1298	1			T8	5		T53	1		T120	444
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53146	1			T53	3418		T49	3161		T101	690
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	598	1			T52	4		T49	2		T99	19
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	61420	1			T52	2		T49	257		T99	594
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	509	1			T8	5		T52	3		T120	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	45105	1			T2	2653		T52	641		T101	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	3161	1			T2	1		T106	103		T52	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	65893	1			T2	314		T53	512		T49	617
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	3546	1			T106	280		T120	896		T49	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46738	1			T99	492		T101	640		T112	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1014	1			T8	14		T52	13		T120	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62205	1			T52	5946		T99	5		T101	771
auto[1]	auto[0]	auto[0:524287]	auto[0]	490	1			T20	4		T60	2		T52	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3142	1			T20	42		T60	10		T52	99
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	387	1			T52	2		T53	1		T109	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2801	1			T52	61		T53	12		T112	8
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	413	1			T52	2		T101	1		T121	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2128	1			T52	70		T101	32		T121	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	452	1			T2	1		T52	1		T49	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3357	1			T52	30		T49	26		T98	26
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	403	1			T52	3		T49	1		T101	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2371	1			T52	58		T49	7		T101	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	339	1			T52	1		T98	3		T101	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2204	1			T52	22		T98	64		T101	42
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	537	1			T52	2		T99	27		T109	21
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2659	1			T52	64		T99	2		T109	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	477	1			T2	3		T52	2		T98	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2547	1			T2	5		T52	56		T98	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	137	1			T53	1		T63	2		T101	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	2735	1			T53	1		T63	4		T101	37
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	88	1			T103	8		T211	3		T167	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	266	1			T103	6		T167	3		T110	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	71	1			T49	1		T101	1		T112	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1134	1			T49	72		T101	12		T112	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	88	1			T52	4		T49	1		T101	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	612	1			T52	33		T49	21		T101	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	64	1			T52	1		T37	1		T38	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	572	1			T52	20		T37	5		T38	72
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	93	1			T49	2		T224	1		T37	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	841	1			T49	35		T224	26		T37	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	87	1			T112	1		T197	1		T209	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	302	1			T112	11		T197	1		T37	42
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	67	1			T52	5		T121	4		T209	16
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	571	1			T52	108		T209	3		T38	51

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2041334	1			T2	13		T7	1		T8	1
auto[0]	auto[0]	auto[1]	1154388	1			T8	5		T9	56		T15	2
auto[0]	auto[1]	auto[0]	477314	1			T2	2968		T8	15		T15	2
auto[0]	auto[1]	auto[1]	9033	1			T8	15		T106	381		T52	5
auto[1]	auto[0]	auto[0]	24110	1			T2	9		T20	44		T60	12
auto[1]	auto[0]	auto[1]	597	1			T20	2		T52	2		T98	3
auto[1]	auto[1]	auto[0]	7624	1			T52	170		T53	2		T49	132
auto[1]	auto[1]	auto[1]	104	1			T52	1		T63	2		T209	1