Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	8	0	8	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_write	2	0	2	100.00	100	1	1	0
cp_payload_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_upload_payload_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	8	0	8	100.00	100	1	1	0

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

753

1

T2

2

T52

12

T49

3

write

1627

1

T2

2

T20

4

T60

2

---

Summary for Variable cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_payload_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
excess_fifo	545	1			T60	2		T52	3		T63	1
frequent_use_values[0]	808	1			T2	2		T52	12		T49	3
frequent_use_values[1]	71	1			T52	3		T121	1		T112	2
frequent_use_values[2]	65	1			T109	1		T37	2		T38	1
frequent_use_values[3]	67	1			T101	1		T124	1		T242	1
frequent_use_values[4]	67	1			T20	4		T99	1		T121	1
frequent_use_values[256]	397	1			T52	3		T53	1		T49	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_payload_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_payload_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read	frequent_use_values[0]	753	1			T2	2		T52	12		T49	3
write	excess_fifo	545	1			T60	2		T52	3		T63	1
write	frequent_use_values[0]	55	1			T101	2		T121	1		T37	1
write	frequent_use_values[1]	71	1			T52	3		T121	1		T112	2
write	frequent_use_values[2]	65	1			T109	1		T37	2		T38	1
write	frequent_use_values[3]	67	1			T101	1		T124	1		T242	1
write	frequent_use_values[4]	67	1			T20	4		T99	1		T121	1
write	frequent_use_values[256]	397	1			T52	3		T53	1		T49	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
read_w_nonzero_payload	0	Illegal