Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2834164	1			T1	1		T2	6257		T3	1
all_pins[1]	2834164	1			T1	1		T2	6257		T3	1
all_pins[2]	2834164	1			T1	1		T2	6257		T3	1
all_pins[3]	2834164	1			T1	1		T2	6257		T3	1
all_pins[4]	2834164	1			T1	1		T2	6257		T3	1
all_pins[5]	2834164	1			T1	1		T2	6257		T3	1
all_pins[6]	2834164	1			T1	1		T2	6257		T3	1
all_pins[7]	2834164	1			T1	1		T2	6257		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22505329	1			T1	8		T2	50056		T3	8
values[0x1]	167983	1			T25	34		T35	55		T36	152
transitions[0x0=>0x1]	167391	1			T25	24		T35	36		T36	111
transitions[0x1=>0x0]	167406	1			T25	24		T35	36		T36	111

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2832943	1			T1	1		T2	6257		T3	1
all_pins[0]	values[0x1]	1221	1			T25	6		T35	8		T36	34
all_pins[0]	transitions[0x0=>0x1]	981	1			T25	3		T35	4		T36	4
all_pins[0]	transitions[0x1=>0x0]	382	1			T25	4		T35	3		T36	5
all_pins[1]	values[0x0]	2833542	1			T1	1		T2	6257		T3	1
all_pins[1]	values[0x1]	622	1			T25	7		T35	7		T36	35
all_pins[1]	transitions[0x0=>0x1]	561	1			T25	5		T35	3		T36	30
all_pins[1]	transitions[0x1=>0x0]	365	1			T25	1		T35	5		T36	2
all_pins[2]	values[0x0]	2833738	1			T1	1		T2	6257		T3	1
all_pins[2]	values[0x1]	426	1			T25	3		T35	9		T36	7
all_pins[2]	transitions[0x0=>0x1]	381	1			T25	1		T35	5		T36	6
all_pins[2]	transitions[0x1=>0x0]	156	1			T25	2		T35	7		T36	6
all_pins[3]	values[0x0]	2833963	1			T1	1		T2	6257		T3	1
all_pins[3]	values[0x1]	201	1			T25	4		T35	11		T36	7
all_pins[3]	transitions[0x0=>0x1]	145	1			T25	4		T35	7		T36	4
all_pins[3]	transitions[0x1=>0x0]	167	1			T25	2		T35	3		T37	2
all_pins[4]	values[0x0]	2833941	1			T1	1		T2	6257		T3	1
all_pins[4]	values[0x1]	223	1			T25	2		T35	7		T36	3
all_pins[4]	transitions[0x0=>0x1]	182	1			T25	2		T35	7		T36	3
all_pins[4]	transitions[0x1=>0x0]	1619	1			T25	3		T35	5		T36	61
all_pins[5]	values[0x0]	2832504	1			T1	1		T2	6257		T3	1
all_pins[5]	values[0x1]	1660	1			T25	3		T35	5		T36	61
all_pins[5]	transitions[0x0=>0x1]	1624	1			T25	3		T35	5		T36	61
all_pins[5]	transitions[0x1=>0x0]	163386	1			T25	4		T35	3		T36	1
all_pins[6]	values[0x0]	2670742	1			T1	1		T2	6257		T3	1
all_pins[6]	values[0x1]	163422	1			T25	4		T35	3		T36	1
all_pins[6]	transitions[0x0=>0x1]	163369	1			T25	4		T35	3		T37	1
all_pins[6]	transitions[0x1=>0x0]	155	1			T25	5		T35	5		T36	3
all_pins[7]	values[0x0]	2833956	1			T1	1		T2	6257		T3	1
all_pins[7]	values[0x1]	208	1			T25	5		T35	5		T36	4
all_pins[7]	transitions[0x0=>0x1]	148	1			T25	2		T35	2		T36	3
all_pins[7]	transitions[0x1=>0x0]	1176	1			T25	3		T35	5		T36	33