Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15626

1

T8

12

T15

4

T16

10

auto[1]

12045

1

T23

2

T56

20

T64

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4016	1			T106	10		T56	20		T48	16
values[1]	3132	1			T105	2		T57	16		T104	6
values[2]	3494	1			T8	12		T18	12		T23	2
values[3]	3042	1			T20	52		T79	4		T67	12
values[4]	3583	1			T51	10		T59	18		T100	69
values[5]	3380	1			T15	4		T64	10		T65	12
values[6]	3645	1			T16	10		T61	4		T66	18
values[7]	3379	1			T58	8		T62	2		T60	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3320	1			T51	10		T104	6		T282	2
values[1]	3097	1			T65	12		T253	2		T288	8
values[2]	3460	1			T15	4		T16	10		T105	2
values[3]	3802	1			T67	12		T283	2		T122	6
values[4]	3470	1			T20	52		T61	4		T164	10
values[5]	3618	1			T23	2		T62	2		T64	10
values[6]	3539	1			T8	12		T18	12		T57	16
values[7]	3365	1			T58	8		T106	10		T56	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	243	1			T38	9		T70	14		T72	6
auto[0]	values[0]	values[1]	180	1			T69	20		T289	12		T277	13
auto[0]	values[0]	values[2]	307	1			T290	11		T291	4		T277	12
auto[0]	values[0]	values[3]	304	1			T193	10		T123	8		T38	12
auto[0]	values[0]	values[4]	306	1			T292	12		T249	21		T277	13
auto[0]	values[0]	values[5]	248	1			T48	16		T239	14		T191	27
auto[0]	values[0]	values[6]	364	1			T111	11		T293	21		T277	10
auto[0]	values[0]	values[7]	375	1			T106	10		T199	229		T123	13
auto[0]	values[1]	values[0]	175	1			T104	6		T70	16		T192	8
auto[0]	values[1]	values[1]	312	1			T253	2		T294	14		T42	22
auto[0]	values[1]	values[2]	273	1			T105	2		T200	10		T231	16
auto[0]	values[1]	values[3]	195	1			T38	31		T167	8		T221	7
auto[0]	values[1]	values[4]	229	1			T191	16		T192	10		T190	8
auto[0]	values[1]	values[5]	285	1			T103	11		T238	20		T256	14
auto[0]	values[1]	values[6]	232	1			T57	16		T70	34		T217	8
auto[0]	values[1]	values[7]	137	1			T124	8		T69	21		T277	9
auto[0]	values[2]	values[0]	235	1			T69	18		T295	4		T38	13
auto[0]	values[2]	values[1]	203	1			T38	7		T93	12		T191	16
auto[0]	values[2]	values[2]	299	1			T123	12		T296	14		T93	41
auto[0]	values[2]	values[3]	292	1			T283	2		T297	4		T298	6
auto[0]	values[2]	values[4]	207	1			T281	22		T276	13		T219	7
auto[0]	values[2]	values[5]	249	1			T263	10		T123	14		T299	4
auto[0]	values[2]	values[6]	168	1			T8	12		T18	12		T187	2
auto[0]	values[2]	values[7]	307	1			T103	19		T167	8		T300	8
auto[0]	values[3]	values[0]	150	1			T301	6		T221	9		T222	10
auto[0]	values[3]	values[1]	80	1			T123	11		T302	4		T303	4
auto[0]	values[3]	values[2]	210	1			T63	5		T216	16		T69	11
auto[0]	values[3]	values[3]	390	1			T67	12		T267	16		T70	13
auto[0]	values[3]	values[4]	262	1			T20	52		T164	10		T38	8
auto[0]	values[3]	values[5]	215	1			T274	10		T223	12		T236	14
auto[0]	values[3]	values[6]	239	1			T79	4		T123	27		T191	61
auto[0]	values[3]	values[7]	142	1			T235	8		T167	13		T245	10
auto[0]	values[4]	values[0]	274	1			T51	10		T304	10		T290	12
auto[0]	values[4]	values[1]	290	1			T288	8		T305	14		T93	14
auto[0]	values[4]	values[2]	240	1			T306	12		T307	121		T111	10
auto[0]	values[4]	values[3]	154	1			T103	12		T69	15		T70	5
auto[0]	values[4]	values[4]	336	1			T308	42		T309	6		T310	24
auto[0]	values[4]	values[5]	314	1			T59	18		T69	7		T275	10
auto[0]	values[4]	values[6]	309	1			T100	69		T311	4		T167	8
auto[0]	values[4]	values[7]	191	1			T69	9		T312	2		T313	20
auto[0]	values[5]	values[0]	318	1			T284	8		T70	8		T273	6
auto[0]	values[5]	values[1]	304	1			T65	12		T280	14		T191	10
auto[0]	values[5]	values[2]	162	1			T15	4		T70	9		T195	10
auto[0]	values[5]	values[3]	142	1			T103	13		T72	13		T191	12
auto[0]	values[5]	values[4]	247	1			T70	11		T262	24		T314	2
auto[0]	values[5]	values[5]	211	1			T215	10		T315	4		T316	4
auto[0]	values[5]	values[6]	295	1			T78	10		T279	14		T219	109
auto[0]	values[5]	values[7]	175	1			T254	14		T219	11		T256	9
auto[0]	values[6]	values[0]	290	1			T261	10		T317	2		T318	12
auto[0]	values[6]	values[1]	229	1			T293	17		T256	16		T183	7
auto[0]	values[6]	values[2]	233	1			T16	10		T290	13		T319	10
auto[0]	values[6]	values[3]	202	1			T123	24		T247	6		T320	34
auto[0]	values[6]	values[4]	128	1			T61	4		T321	8		T243	18
auto[0]	values[6]	values[5]	237	1			T120	10		T249	16		T111	21
auto[0]	values[6]	values[6]	209	1			T192	13		T42	25		T170	21
auto[0]	values[6]	values[7]	392	1			T72	49		T192	16		T322	8
auto[0]	values[7]	values[0]	178	1			T282	2		T323	6		T111	10
auto[0]	values[7]	values[1]	204	1			T192	8		T194	14		T320	12
auto[0]	values[7]	values[2]	168	1			T103	13		T70	20		T324	14
auto[0]	values[7]	values[3]	414	1			T122	6		T50	10		T213	12
auto[0]	values[7]	values[4]	205	1			T123	13		T325	4		T326	11
auto[0]	values[7]	values[5]	273	1			T62	2		T60	20		T81	16
auto[0]	values[7]	values[6]	317	1			T69	12		T38	9		T327	11
auto[0]	values[7]	values[7]	172	1			T58	8		T328	6		T256	12
auto[1]	values[0]	values[0]	217	1			T38	56		T70	17		T72	14
auto[1]	values[0]	values[1]	120	1			T69	33		T277	7		T329	13
auto[1]	values[0]	values[2]	189	1			T290	9		T277	15		T222	17
auto[1]	values[0]	values[3]	239	1			T123	12		T38	82		T70	6
auto[1]	values[0]	values[4]	342	1			T330	26		T249	5		T331	2
auto[1]	values[0]	values[5]	216	1			T191	37		T290	59		T194	8
auto[1]	values[0]	values[6]	184	1			T111	48		T293	8		T277	10
auto[1]	values[0]	values[7]	182	1			T56	20		T123	7		T276	10
auto[1]	values[1]	values[0]	150	1			T70	11		T192	12		T222	17
auto[1]	values[1]	values[1]	115	1			T294	12		T42	11		T332	7
auto[1]	values[1]	values[2]	114	1			T333	16		T194	8		T221	15
auto[1]	values[1]	values[3]	161	1			T38	9		T167	12		T221	13
auto[1]	values[1]	values[4]	165	1			T191	4		T192	10		T190	12
auto[1]	values[1]	values[5]	154	1			T103	9		T256	6		T221	7
auto[1]	values[1]	values[6]	298	1			T70	8		T334	10		T93	20
auto[1]	values[1]	values[7]	137	1			T124	16		T69	11		T335	8
auto[1]	values[2]	values[0]	151	1			T69	11		T38	7		T72	3
auto[1]	values[2]	values[1]	132	1			T38	26		T93	8		T191	4
auto[1]	values[2]	values[2]	225	1			T123	8		T93	14		T276	11
auto[1]	values[2]	values[3]	298	1			T73	18		T191	40		T336	11
auto[1]	values[2]	values[4]	337	1			T276	7		T219	75		T223	6
auto[1]	values[2]	values[5]	203	1			T23	2		T123	6		T167	4
auto[1]	values[2]	values[6]	73	1			T69	9		T257	14		T192	10
auto[1]	values[2]	values[7]	115	1			T103	1		T337	12		T167	16
auto[1]	values[3]	values[0]	142	1			T259	24		T221	11		T222	10
auto[1]	values[3]	values[1]	126	1			T123	9		T338	16		T274	13
auto[1]	values[3]	values[2]	215	1			T63	21		T69	9		T276	15
auto[1]	values[3]	values[3]	240	1			T70	9		T72	7		T167	11
auto[1]	values[3]	values[4]	178	1			T38	15		T276	6		T190	8
auto[1]	values[3]	values[5]	158	1			T274	10		T223	8		T236	6
auto[1]	values[3]	values[6]	162	1			T123	13		T191	67		T320	8
auto[1]	values[3]	values[7]	133	1			T71	14		T167	7		T245	14
auto[1]	values[4]	values[0]	126	1			T290	8		T194	7		T222	8
auto[1]	values[4]	values[1]	210	1			T93	8		T339	16		T170	12
auto[1]	values[4]	values[2]	117	1			T307	13		T111	22		T277	8
auto[1]	values[4]	values[3]	164	1			T103	8		T69	5		T70	15
auto[1]	values[4]	values[4]	164	1			T198	8		T307	6		T340	6
auto[1]	values[4]	values[5]	400	1			T69	13		T275	10		T111	27
auto[1]	values[4]	values[6]	133	1			T74	28		T167	25		T111	15
auto[1]	values[4]	values[7]	161	1			T69	11		T307	8		T194	18
auto[1]	values[5]	values[0]	204	1			T70	25		T276	7		T190	7
auto[1]	values[5]	values[1]	191	1			T191	12		T219	10		T221	9
auto[1]	values[5]	values[2]	128	1			T70	15		T195	39		T277	10
auto[1]	values[5]	values[3]	197	1			T103	7		T72	7		T191	8
auto[1]	values[5]	values[4]	188	1			T225	8		T70	13		T236	8
auto[1]	values[5]	values[5]	199	1			T64	10		T341	10		T219	12
auto[1]	values[5]	values[6]	232	1			T279	6		T219	24		T293	9
auto[1]	values[5]	values[7]	187	1			T219	16		T256	43		T332	13
auto[1]	values[6]	values[0]	232	1			T249	12		T274	23		T245	6
auto[1]	values[6]	values[1]	270	1			T293	13		T256	4		T183	13
auto[1]	values[6]	values[2]	323	1			T290	7		T219	31		T42	6
auto[1]	values[6]	values[3]	215	1			T123	16		T247	74		T320	15
auto[1]	values[6]	values[4]	80	1			T93	8		T249	22		T221	7
auto[1]	values[6]	values[5]	163	1			T249	4		T111	31		T222	9
auto[1]	values[6]	values[6]	181	1			T68	22		T192	7		T42	6
auto[1]	values[6]	values[7]	261	1			T66	18		T72	10		T192	4
auto[1]	values[7]	values[0]	235	1			T111	10		T245	10		T223	8
auto[1]	values[7]	values[1]	131	1			T192	12		T194	14		T320	11
auto[1]	values[7]	values[2]	257	1			T103	7		T70	7		T190	10
auto[1]	values[7]	values[3]	195	1			T191	5		T192	8		T249	5
auto[1]	values[7]	values[4]	96	1			T123	7		T326	9		T320	16
auto[1]	values[7]	values[5]	93	1			T103	7		T326	5		T274	7
auto[1]	values[7]	values[6]	143	1			T69	8		T38	21		T327	9
auto[1]	values[7]	values[7]	298	1			T256	8		T221	57		T222	13