Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	308	1			T57	8		T79	2		T48	4
auto[ReadAddrCrossIntoMailbox]	251	1			T48	4		T282	2		T69	2
auto[ReadAddrCrossOutOfMailbox]	267	1			T48	2		T124	1		T200	2
auto[ReadAddrCrossAllMailbox]	220	1			T48	6		T63	1		T124	2
auto[ReadAddrOutsideMailbox]	3127	1			T16	4		T18	8		T51	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2125

1

T16

2

T18

4

T51

5

auto[1]

2048

1

T16

2

T18

4

T51

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	657	1			T58	2		T57	4		T48	4
read_ops[0x0b]	672	1			T18	4		T81	4		T48	2
read_ops[0x3b]	689	1			T51	6		T57	2		T104	2
read_ops[0x6b]	736	1			T16	4		T51	4		T56	2
read_ops[0xbb]	704	1			T18	2		T61	2		T81	4
read_ops[0xeb]	715	1			T18	2		T56	2		T57	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T57	2		T48	1		T50	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T57	2		T48	1		T50	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T48	1		T274	2		T223	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T48	1		T256	1		T221	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T192	1		T326	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T93	1		T111	1		T277	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T253	1		T69	1		T70	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T253	1		T38	1		T190	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T58	1		T216	1		T103	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T58	1		T216	1		T103	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T281	1		T38	1		T93	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T281	1		T219	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T262	1		T276	1		T256	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T262	1		T191	1		T290	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T191	1		T194	1		T111	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T38	1		T290	1		T194	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T48	1		T262	2		T256	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T48	1		T123	1		T262	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T18	2		T81	2		T63	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T18	2		T81	2		T103	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T57	1		T79	1		T281	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T57	1		T79	1		T281	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T123	1		T300	1		T221	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T247	1		T191	2		T290	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T200	1		T343	2		T274	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T200	1		T38	2		T327	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T200	1		T70	1		T262	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T200	1		T123	1		T262	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T51	3		T104	1		T59	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T51	3		T104	1		T59	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T124	1		T281	2		T123	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T103	1		T281	2		T295	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T302	1		T192	1		T277	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T247	1		T302	1		T326	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T123	1		T167	1		T93	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T38	1		T93	1		T320	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T200	1		T69	1		T123	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T63	1		T200	1		T191	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T16	2		T51	2		T56	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T16	2		T51	2		T56	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T123	1		T280	1		T262	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T69	1		T280	1		T262	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T282	1		T262	1		T191	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T282	1		T69	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T124	1		T123	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T123	1		T280	1		T167	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T124	1		T70	2		T314	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T191	1		T293	1		T256	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T18	1		T61	1		T81	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T18	1		T61	1		T81	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T57	1		T48	1		T283	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T57	1		T48	1		T283	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T48	1		T38	1		T280	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T48	1		T69	1		T123	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T48	1		T280	1		T309	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T48	1		T38	1		T280	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T48	2		T124	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T48	2		T200	1		T123	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T18	1		T56	1		T78	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T18	1		T56	1		T78	1