Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3844	1			T64	10		T59	18		T60	20
values[1]	3383	1			T15	4		T16	10		T23	2
values[2]	3271	1			T187	2		T61	4		T100	69
values[3]	3317	1			T8	12		T20	52		T51	10
values[4]	3397	1			T106	10		T105	2		T216	16
values[5]	3510	1			T56	20		T104	6		T65	12
values[6]	3921	1			T58	8		T67	12		T164	10
values[7]	3028	1			T18	12		T50	10		T282	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3799	1			T106	10		T60	20		T79	4
values[1]	3074	1			T56	20		T64	10		T66	18
values[2]	3494	1			T57	16		T215	10		T198	8
values[3]	3076	1			T120	10		T193	10		T216	16
values[4]	3809	1			T23	2		T63	26		T124	24
values[5]	3774	1			T8	12		T16	10		T18	12
values[6]	2859	1			T61	4		T62	2		T78	10
values[7]	3786	1			T15	4		T51	10		T104	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26889

1

T8

12

T15

4

T16

10

auto[1]

782

1

T66

6

T63

2

T124

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	463	1			T60	20		T72	57		T93	20
auto[0]	values[0]	values[1]	475	1			T64	10		T71	6		T70	57
auto[0]	values[0]	values[2]	419	1			T123	19		T191	22		T290	87
auto[0]	values[0]	values[3]	464	1			T280	14		T267	16		T249	22
auto[0]	values[0]	values[4]	432	1			T63	24		T295	4		T38	65
auto[0]	values[0]	values[5]	551	1			T283	2		T259	24		T72	20
auto[0]	values[0]	values[6]	459	1			T232	10		T223	19		T222	20
auto[0]	values[0]	values[7]	464	1			T59	18		T69	20		T298	6
auto[0]	values[1]	values[0]	216	1			T123	20		T344	10		T345	8
auto[0]	values[1]	values[1]	490	1			T200	10		T341	10		T277	21
auto[0]	values[1]	values[2]	450	1			T57	16		T334	10		T217	8
auto[0]	values[1]	values[3]	375	1			T275	20		T299	4		T316	4
auto[0]	values[1]	values[4]	361	1			T23	2		T69	20		T38	93
auto[0]	values[1]	values[5]	276	1			T16	10		T69	20		T234	24
auto[0]	values[1]	values[6]	301	1			T62	2		T69	50		T191	20
auto[0]	values[1]	values[7]	824	1			T15	4		T199	229		T123	20
auto[0]	values[2]	values[0]	708	1			T281	22		T297	4		T340	6
auto[0]	values[2]	values[1]	392	1			T305	14		T191	20		T221	20
auto[0]	values[2]	values[2]	516	1			T247	78		T191	71		T111	86
auto[0]	values[2]	values[3]	66	1			T314	2		T223	20		T346	20
auto[0]	values[2]	values[4]	384	1			T124	22		T38	20		T70	24
auto[0]	values[2]	values[5]	693	1			T187	2		T100	69		T347	10
auto[0]	values[2]	values[6]	273	1			T61	4		T212	4		T222	35
auto[0]	values[2]	values[7]	159	1			T348	24		T301	6		T331	2
auto[0]	values[3]	values[0]	651	1			T79	4		T69	20		T292	12
auto[0]	values[3]	values[1]	365	1			T66	12		T81	16		T69	20
auto[0]	values[3]	values[2]	315	1			T190	20		T349	4		T350	22
auto[0]	values[3]	values[3]	413	1			T69	28		T321	8		T191	41
auto[0]	values[3]	values[4]	515	1			T93	26		T336	20		T255	26
auto[0]	values[3]	values[5]	304	1			T8	12		T20	52		T38	33
auto[0]	values[3]	values[6]	261	1			T78	10		T195	65		T320	20
auto[0]	values[3]	values[7]	383	1			T51	10		T68	12		T123	20
auto[0]	values[4]	values[0]	347	1			T106	10		T288	8		T123	20
auto[0]	values[4]	values[1]	258	1			T225	8		T254	14		T222	16
auto[0]	values[4]	values[2]	277	1			T312	2		T219	20		T190	20
auto[0]	values[4]	values[3]	607	1			T216	16		T103	40		T323	6
auto[0]	values[4]	values[4]	597	1			T317	2		T307	130		T249	20
auto[0]	values[4]	values[5]	408	1			T105	2		T69	31		T167	38
auto[0]	values[4]	values[6]	279	1			T103	20		T306	12		T42	68
auto[0]	values[4]	values[7]	529	1			T253	2		T93	21		T192	40
auto[0]	values[5]	values[0]	346	1			T93	34		T191	52		T221	48
auto[0]	values[5]	values[1]	344	1			T56	20		T122	6		T123	20
auto[0]	values[5]	values[2]	442	1			T215	10		T198	8		T311	4
auto[0]	values[5]	values[3]	360	1			T120	10		T193	10		T342	8
auto[0]	values[5]	values[4]	503	1			T304	10		T191	71		T192	19
auto[0]	values[5]	values[5]	406	1			T239	14		T70	85		T219	79
auto[0]	values[5]	values[6]	581	1			T48	16		T103	20		T296	14
auto[0]	values[5]	values[7]	411	1			T104	6		T65	12		T69	20
auto[0]	values[6]	values[0]	601	1			T67	12		T325	4		T351	2
auto[0]	values[6]	values[1]	307	1			T164	10		T263	10		T123	20
auto[0]	values[6]	values[2]	754	1			T167	19		T93	20		T290	20
auto[0]	values[6]	values[3]	194	1			T38	27		T273	6		T223	18
auto[0]	values[6]	values[4]	609	1			T38	20		T308	42		T70	21
auto[0]	values[6]	values[5]	519	1			T58	8		T235	8		T191	30
auto[0]	values[6]	values[6]	368	1			T103	20		T302	4		T327	20
auto[0]	values[6]	values[7]	472	1			T324	14		T93	19		T219	113
auto[0]	values[7]	values[0]	382	1			T282	2		T123	20		T352	6
auto[0]	values[7]	values[1]	363	1			T103	20		T284	8		T195	49
auto[0]	values[7]	values[2]	220	1			T191	20		T353	2		T354	20
auto[0]	values[7]	values[3]	496	1			T70	29		T243	18		T194	20
auto[0]	values[7]	values[4]	282	1			T320	29		T42	24		T43	20
auto[0]	values[7]	values[5]	517	1			T18	12		T50	10		T38	20
auto[0]	values[7]	values[6]	252	1			T355	14		T221	45		T274	20
auto[0]	values[7]	values[7]	440	1			T356	6		T167	23		T111	20
auto[1]	values[0]	values[0]	14	1			T72	2		T93	1		T194	1
auto[1]	values[0]	values[1]	15	1			T71	8		T70	3		T237	3
auto[1]	values[0]	values[2]	15	1			T123	1		T290	6		T274	1
auto[1]	values[0]	values[3]	12	1			T249	4		T320	1		T357	1
auto[1]	values[0]	values[4]	20	1			T63	2		T245	1		T222	6
auto[1]	values[0]	values[5]	7	1			T111	1		T329	2		T358	1
auto[1]	values[0]	values[6]	19	1			T223	1		T329	1		T357	1
auto[1]	values[0]	values[7]	15	1			T335	2		T320	2		T248	1
auto[1]	values[1]	values[0]	4	1			T183	2		T230	1		T359	1
auto[1]	values[1]	values[1]	8	1			T274	1		T350	4		T170	2
auto[1]	values[1]	values[2]	16	1			T326	3		T221	1		T171	3
auto[1]	values[1]	values[3]	13	1			T330	4		T277	1		T294	2
auto[1]	values[1]	values[4]	12	1			T38	1		T70	2		T73	2
auto[1]	values[1]	values[5]	9	1			T279	1		T221	3		T42	4
auto[1]	values[1]	values[6]	13	1			T69	2		T221	1		T350	4
auto[1]	values[1]	values[7]	15	1			T192	1		T274	1		T360	4
auto[1]	values[2]	values[0]	13	1			T350	1		T358	1		T244	1
auto[1]	values[2]	values[1]	7	1			T332	4		T361	2		T362	1
auto[1]	values[2]	values[2]	13	1			T247	2		T363	2		T358	1
auto[1]	values[2]	values[3]	1	1			T346	1		-	-		-	-
auto[1]	values[2]	values[4]	14	1			T124	2		T307	1		T364	4
auto[1]	values[2]	values[5]	21	1			T219	1		T350	1		T365	1
auto[1]	values[2]	values[6]	6	1			T332	2		T366	2		T367	1
auto[1]	values[2]	values[7]	5	1			T223	2		T368	2		T346	1
auto[1]	values[3]	values[0]	19	1			T276	2		T222	2		T360	3
auto[1]	values[3]	values[1]	15	1			T66	6		T194	2		T221	1
auto[1]	values[3]	values[2]	9	1			T350	1		T332	1		T369	2
auto[1]	values[3]	values[3]	13	1			T69	1		T191	3		T111	1
auto[1]	values[3]	values[4]	17	1			T43	3		T370	6		T237	2
auto[1]	values[3]	values[5]	3	1			T371	2		T372	1		-	-
auto[1]	values[3]	values[6]	11	1			T195	1		T320	3		T42	2
auto[1]	values[3]	values[7]	23	1			T68	10		T221	1		T320	4
auto[1]	values[4]	values[0]	8	1			T72	1		T373	3		T374	4
auto[1]	values[4]	values[1]	7	1			T222	4		T248	2		T375	1
auto[1]	values[4]	values[2]	2	1			T376	1		T377	1		-	-
auto[1]	values[4]	values[3]	28	1			T293	1		T222	1		T42	3
auto[1]	values[4]	values[4]	16	1			T307	4		T245	1		T329	1
auto[1]	values[4]	values[5]	12	1			T69	2		T167	3		T236	1
auto[1]	values[4]	values[6]	4	1			T260	1		T378	3		-	-
auto[1]	values[4]	values[7]	18	1			T93	1		T293	2		T248	1
auto[1]	values[5]	values[0]	9	1			T277	2		T42	4		T260	1
auto[1]	values[5]	values[1]	11	1			T379	1		T380	1		T381	5
auto[1]	values[5]	values[2]	22	1			T74	10		T230	2		T237	3
auto[1]	values[5]	values[3]	13	1			T192	5		T245	4		T294	2
auto[1]	values[5]	values[4]	23	1			T191	6		T192	1		T194	5
auto[1]	values[5]	values[5]	8	1			T70	1		T111	1		T293	1
auto[1]	values[5]	values[6]	22	1			T111	2		T293	2		T256	2
auto[1]	values[5]	values[7]	9	1			T123	4		T72	1		T191	1
auto[1]	values[6]	values[0]	13	1			T382	2		T329	1		T383	1
auto[1]	values[6]	values[1]	9	1			T249	2		T194	1		T256	1
auto[1]	values[6]	values[2]	13	1			T167	1		T294	1		T332	2
auto[1]	values[6]	values[3]	9	1			T38	3		T223	2		T384	1
auto[1]	values[6]	values[4]	11	1			T70	1		T320	1		T350	5
auto[1]	values[6]	values[5]	26	1			T191	3		T333	6		T194	2
auto[1]	values[6]	values[6]	6	1			T294	1		T366	1		T359	2
auto[1]	values[6]	values[7]	10	1			T93	1		T43	2		T378	2
auto[1]	values[7]	values[0]	5	1			T294	1		T369	1		T248	1
auto[1]	values[7]	values[1]	8	1			T366	2		T380	4		T385	1
auto[1]	values[7]	values[2]	11	1			T320	3		T386	1		T362	3
auto[1]	values[7]	values[3]	12	1			T70	2		T190	2		T256	1
auto[1]	values[7]	values[4]	13	1			T230	1		T379	3		T387	3
auto[1]	values[7]	values[5]	14	1			T38	3		T167	4		T293	2
auto[1]	values[7]	values[6]	4	1			T388	2		T372	2		-	-
auto[1]	values[7]	values[7]	9	1			T167	1		T294	3		T357	2