Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	858	1			T25	15		T35	25		T36	14
all_values[1]	858	1			T25	15		T35	25		T36	14
all_values[2]	858	1			T25	15		T35	25		T36	14
all_values[3]	858	1			T25	15		T35	25		T36	14
all_values[4]	858	1			T25	15		T35	25		T36	14
all_values[5]	858	1			T25	15		T35	25		T36	14
all_values[6]	858	1			T25	15		T35	25		T36	14
all_values[7]	858	1			T25	15		T35	25		T36	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3590

1

T25

66

T35

85

T36

41

auto[1]

3274

1

T25

54

T35

115

T36

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2724

1

T25

46

T35

84

T36

39

auto[1]

4140

1

T25

74

T35

116

T36

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3857

1

T25

67

T35

119

T36

58

auto[1]

3007

1

T25

53

T35

81

T36

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	197	1			T25	3		T35	7		T36	1
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T35	1		T36	1		T189	2
all_values[0]	auto[0]	auto[1]	auto[0]	145	1			T25	1		T35	6		T36	5
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T25	2		T35	4		T36	1
all_values[0]	auto[1]	auto[0]	auto[1]	195	1			T25	7		T35	5		T36	1
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T25	2		T35	2		T36	5
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T25	3		T35	3		T37	2
all_values[1]	auto[0]	auto[0]	auto[1]	69	1			T35	1		T36	1		T37	1
all_values[1]	auto[0]	auto[1]	auto[0]	161	1			T25	1		T35	8		T36	3
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T25	3		T35	2		T36	2
all_values[1]	auto[1]	auto[0]	auto[1]	200	1			T25	2		T35	4		T36	3
all_values[1]	auto[1]	auto[1]	auto[1]	176	1			T25	6		T35	7		T36	5
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T25	4		T35	5		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	67	1			T25	1		T37	1		T189	2
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T25	2		T35	7		T36	4
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T25	2		T35	5		T36	2
all_values[2]	auto[1]	auto[0]	auto[1]	202	1			T25	5		T35	3		T36	2
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T25	1		T35	5		T36	5
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T25	4		T35	3		T36	2
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T25	2		T35	2		T37	5
all_values[3]	auto[0]	auto[1]	auto[0]	146	1			T35	3		T189	7		T70	4
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T25	3		T35	4		T36	3
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T25	4		T35	3		T36	6
all_values[3]	auto[1]	auto[1]	auto[1]	168	1			T25	2		T35	10		T36	3
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T25	6		T35	1		T36	5
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T25	2		T35	4		T37	1
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T25	1		T35	6		T36	3
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T25	1		T35	4		T36	2
all_values[4]	auto[1]	auto[0]	auto[1]	205	1			T25	4		T35	2		T36	3
all_values[4]	auto[1]	auto[1]	auto[1]	194	1			T25	1		T35	8		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T25	5		T35	4		T37	4
all_values[5]	auto[0]	auto[1]	auto[0]	252	1			T25	5		T35	11		T36	8
all_values[5]	auto[1]	auto[0]	auto[1]	201	1			T25	3		T35	5		T37	1
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T25	2		T35	5		T36	6
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T25	1		T35	4		T37	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T25	2		T35	3		T36	3
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T25	4		T35	4		T36	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T35	2		T37	1		T189	2
all_values[6]	auto[1]	auto[0]	auto[1]	225	1			T25	3		T35	9		T36	6
all_values[6]	auto[1]	auto[1]	auto[1]	172	1			T25	5		T35	3		T36	3
all_values[7]	auto[0]	auto[0]	auto[0]	174	1			T25	1		T35	8		T36	3
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T25	1		T35	2		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T25	5		T35	4		T36	2
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T25	2		T35	1		T36	2
all_values[7]	auto[1]	auto[0]	auto[1]	199	1			T25	3		T35	6		T36	1
all_values[7]	auto[1]	auto[1]	auto[1]	173	1			T25	3		T35	4		T36	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal