Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1741

1

T2

1

T5

2

T12

8

auto[1]

1694

1

T2

2

T5

1

T12

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T2

2

T14

2

T29

11

auto[1]

1545

1

T2

1

T5

3

T12

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2713

1

T2

1

T5

3

T12

10

auto[1]

722

1

T2

2

T14

1

T29

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	641	1			T17	8		T28	6		T29	2
valid[1]	675	1			T2	1		T5	1		T12	2
valid[2]	727	1			T2	1		T12	3		T14	3
valid[3]	655	1			T5	1		T12	2		T17	12
valid[4]	737	1			T2	1		T5	1		T12	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	102	1			T29	1		T25	1		T53	1
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T17	3		T30	1		T119	2
auto[0]	auto[0]	valid[1]	auto[0]	111	1			T83	2		T53	1		T116	1
auto[0]	auto[0]	valid[1]	auto[1]	157	1			T12	2		T17	4		T28	3
auto[0]	auto[0]	valid[2]	auto[0]	130	1			T29	1		T25	4		T82	1
auto[0]	auto[0]	valid[2]	auto[1]	161	1			T12	2		T14	1		T17	4
auto[0]	auto[0]	valid[3]	auto[0]	119	1			T29	1		T116	3		T124	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T5	1		T12	1		T17	6
auto[0]	auto[0]	valid[4]	auto[0]	136	1			T25	2		T82	1		T83	1
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T5	1		T12	3		T17	3
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T53	1		T101	1		T196	1
auto[0]	auto[1]	valid[0]	auto[1]	144	1			T17	5		T28	6		T30	1
auto[0]	auto[1]	valid[1]	auto[0]	115	1			T29	1		T25	1		T53	1
auto[0]	auto[1]	valid[1]	auto[1]	149	1			T5	1		T17	6		T30	1
auto[0]	auto[1]	valid[2]	auto[0]	114	1			T14	1		T29	1		T83	1
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T12	1		T17	5		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	107	1			T82	1		T83	2		T117	1
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T12	1		T17	6		T28	1
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T25	2		T82	1		T116	1
auto[0]	auto[1]	valid[4]	auto[1]	143	1			T2	1		T17	3		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	66	1			T29	1		T82	1		T197	1
auto[1]	auto[0]	valid[1]	auto[0]	59	1			T29	1		T82	1		T101	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T2	1		T25	1		T196	1
auto[1]	auto[0]	valid[3]	auto[0]	63	1			T29	1		T25	2		T421	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T29	1		T101	2		T196	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T25	1		T53	1		T101	1
auto[1]	auto[1]	valid[1]	auto[0]	84	1			T2	1		T29	2		T82	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T14	1		T82	1		T124	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T82	1		T117	1		T197	1
auto[1]	auto[1]	valid[4]	auto[0]	67	1			T25	1		T82	1		T83	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal