Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50049

1

T2

129

T4

1

T14

62

auto[1]

15990

1

T2

34

T5

3

T12

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47854

1

T2

112

T4

1

T5

3

auto[1]

18185

1

T2

51

T14

22

T29

112

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33975	1			T2	85		T4	1		T5	3
others[1]	5601	1			T2	13		T14	8		T17	59
others[2]	5573	1			T2	8		T14	4		T17	30
others[3]	6344	1			T2	17		T14	7		T17	42
interest[1]	3621	1			T2	14		T14	5		T17	28
interest[4]	22208	1			T2	64		T5	3		T12	10
interest[64]	10925	1			T2	26		T14	14		T17	68

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16441	1			T2	34		T4	1		T14	19
auto[0]	auto[0]	others[1]	2677	1			T2	7		T14	6		T29	18
auto[0]	auto[0]	others[2]	2697	1			T2	6		T14	2		T29	13
auto[0]	auto[0]	others[3]	3107	1			T2	11		T14	6		T29	17
auto[0]	auto[0]	interest[1]	1724	1			T2	7		T14	2		T29	6
auto[0]	auto[0]	interest[4]	10711	1			T2	25		T14	11		T29	83
auto[0]	auto[0]	interest[64]	5218	1			T2	13		T14	5		T29	32
auto[0]	auto[1]	others[0]	8204	1			T2	17		T5	3		T12	10
auto[0]	auto[1]	others[1]	1363	1			T2	5		T14	1		T17	59
auto[0]	auto[1]	others[2]	1301	1			T17	30		T28	24		T29	3
auto[0]	auto[1]	others[3]	1483	1			T2	3		T14	1		T17	42
auto[0]	auto[1]	interest[1]	887	1			T2	3		T14	1		T17	28
auto[0]	auto[1]	interest[4]	5432	1			T2	12		T5	3		T12	10
auto[0]	auto[1]	interest[64]	2752	1			T2	6		T14	4		T17	68
auto[1]	auto[0]	others[0]	9330	1			T2	34		T14	12		T29	56
auto[1]	auto[0]	others[1]	1561	1			T2	1		T14	1		T29	11
auto[1]	auto[0]	others[2]	1575	1			T2	2		T14	2		T29	7
auto[1]	auto[0]	others[3]	1754	1			T2	3		T29	9		T25	15
auto[1]	auto[0]	interest[1]	1010	1			T2	4		T14	2		T29	9
auto[1]	auto[0]	interest[4]	6065	1			T2	27		T14	9		T29	38
auto[1]	auto[0]	interest[64]	2955	1			T2	7		T14	5		T29	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal