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 LINE       19544
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T11
1	1	Covered	T6,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T8,T15

 LINE       19544
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T16,T18
1	1	Covered	T2,T8,T16

 LINE       19544
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T7,T8

 LINE       19544
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T134

 LINE       19544
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T9
1	1	Covered	T16,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T20,T22
1	1	Covered	T2,T20,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T20,T21
1	1	Covered	T2,T20,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T20,T60
1	1	Covered	T2,T20,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T52,T78
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T134

 LINE       19544
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T5,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T6,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T6,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T65,T134

 LINE       19544
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T22,T65

 LINE       19544
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T6,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T64,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T64,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T10
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T10
1	1	Covered	T2,T21,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T15
1	1	Covered	T2,T21,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T8,T15
1	1	Covered	T2,T6,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T21,T65
1	1	Covered	T21,T22,T59

 LINE       19544
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T21,T48

 LINE       19544
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T21
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T5,T12
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T5,T12
1	1	Covered	T2,T59,T134

 LINE       19544
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T5,T12
1	1	Covered	T2,T16,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T64,T75

 LINE       19544
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T21,T133

 LINE       19544
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T16,T21

 LINE       19544
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T17
1	1	Covered	T2,T21,T22

 LINE       19544
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T14,T21
1	1	Covered	T2,T4,T14

 LINE       19544
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T14
1	1	Covered	T2,T16,T21

 LINE       19621
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T135,T136,T137
1	1	1	Covered	T2,T4,T14

 LINE       19636
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T21,T25
1	1	0	Covered	T125,T135,T137
1	1	1	Covered	T25,T35,T36

 LINE       19653
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T21,T22
1	1	0	Covered	T138,T139,T140
1	1	1	Covered	T25,T35,T36

 LINE       19670
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T26,T16
1	1	0	Covered	T135,T136,T137
1	1	1	Covered	T26,T40,T107

 LINE       19673
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T125,T135,T136
1	1	1	Covered	T2,T7,T8

 LINE       19680
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T125,T137,T138
1	1	1	Covered	T2,T8,T9

 LINE       19687
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T27

 LINE       19688
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T135,T136,T137
1	1	1	Covered	T2,T8,T9

 LINE       19697
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T15

 LINE       19698
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T125,T126,T137
1	1	1	Covered	T2,T7,T8

 LINE       19701
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T8,T16
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T16

 LINE       19702
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       19703
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T125,T126,T128
1	1	1	Covered	T2,T8,T9

 LINE       19710
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T125,T135,T136
1	1	1	Covered	T2,T7,T8

 LINE       19715
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T128,T136,T137
1	1	1	Covered	T2,T7,T8

 LINE       19720
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T8,T9
1	1	0	Covered	T128,T135,T137
1	1	1	Covered	T2,T8,T9

 LINE       19723
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T135,T141,T142
1	1	1	Covered	T2,T7,T8

 LINE       19726
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T20,T21
1	1	0	Not Covered
1	1	1	Covered	T2,T20,T60

 LINE       19727
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T21,T64
1	1	0	Not Covered
1	1	1	Covered	T2,T52,T53

 LINE       19728
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T128,T137,T138
1	1	1	Covered	T2,T7,T8