Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2378937	1			T1	1		T3	1		T4	1
all_values[1]	2378937	1			T1	1		T3	1		T4	1
all_values[2]	2378937	1			T1	1		T3	1		T4	1
all_values[3]	2378937	1			T1	1		T3	1		T4	1
all_values[4]	2378937	1			T1	1		T3	1		T4	1
all_values[5]	2378937	1			T1	1		T3	1		T4	1
all_values[6]	2378937	1			T1	1		T3	1		T4	1
all_values[7]	2378937	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18691814

1

T1

8

T3

8

T4

8

auto[1]

339682

1

T34

32

T35

2885

T36

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19005097

1

T1

8

T3

8

T4

8

auto[1]

26399

1

T67

34

T103

129

T48

138

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2341896	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	12414	1			T67	34		T103	43		T48	72
all_values[0]	auto[1]	auto[0]	24394	1			T34	4		T35	476		T37	3
all_values[0]	auto[1]	auto[1]	233	1			T34	1		T35	2		T36	4
all_values[1]	auto[0]	auto[0]	2364638	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	8324	1			T103	43		T48	55		T109	19
all_values[1]	auto[1]	auto[0]	5708	1			T34	2		T35	476		T36	4
all_values[1]	auto[1]	auto[1]	267	1			T34	1		T35	3		T37	3
all_values[2]	auto[0]	auto[0]	2364206	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	3024	1			T103	43		T48	11		T109	4
all_values[2]	auto[1]	auto[0]	11478	1			T34	5		T35	477		T36	1
all_values[2]	auto[1]	auto[1]	229	1			T35	3		T36	4		T37	3
all_values[3]	auto[0]	auto[0]	2284454	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	199	1			T169	1		T34	5		T194	1
all_values[3]	auto[1]	auto[0]	94091	1			T34	1		T35	480		T36	1
all_values[3]	auto[1]	auto[1]	193	1			T34	1		T36	1		T37	4
all_values[4]	auto[0]	auto[0]	2358304	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	200	1			T35	2		T36	1		T37	9
all_values[4]	auto[1]	auto[0]	20257	1			T34	2		T35	4		T36	6
all_values[4]	auto[1]	auto[1]	176	1			T34	1		T35	2		T36	1
all_values[5]	auto[0]	auto[0]	2341734	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	178	1			T34	1		T35	3		T36	2
all_values[5]	auto[1]	auto[0]	36851	1			T34	3		T35	1		T36	3
all_values[5]	auto[1]	auto[1]	174	1			T34	2		T35	2		T36	2
all_values[6]	auto[0]	auto[0]	2282920	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	199	1			T34	1		T35	1		T36	1
all_values[6]	auto[1]	auto[0]	95611	1			T34	2		T35	476		T36	3
all_values[6]	auto[1]	auto[1]	207	1			T34	3		T35	2		T37	7
all_values[7]	auto[0]	auto[0]	2328925	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	199	1			T34	4		T35	3		T36	1
all_values[7]	auto[1]	auto[0]	49630	1			T34	3		T35	481		T37	8
all_values[7]	auto[1]	auto[1]	183	1			T34	1		T37	4		T196	1