Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36185	1			T23	16		T24	6		T25	6
auto[SpiFlashAddrCfg]	7910	1			T13	2		T20	4		T22	1
auto[SpiFlashAddr3b]	9261	1			T13	2		T19	6		T20	8
auto[SpiFlashAddr4b]	7783	1			T13	2		T16	6		T19	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34715

1

T13

6

T19

10

T20

14

auto[1]

26424

1

T16

6

T62

18

T66

26

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32048

1

T13

6

T19

6

T20

12

auto[1]

29091

1

T16

6

T19

4

T20

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41105	1			T16	6		T19	4		T20	2
values[1]	1226	1			T66	4		T126	2		T52	1
values[2]	1550	1			T20	2		T111	4		T55	2
values[3]	1406	1			T19	2		T57	2		T111	2
values[4]	1469	1			T19	4		T57	2		T56	6
values[5]	1559	1			T22	3		T64	6		T145	2
values[6]	1491	1			T57	4		T60	2		T79	2
values[7]	1341	1			T145	1		T65	2		T105	2
values[8]	9992	1			T13	6		T20	10		T24	12

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29858

1

T13

6

T16

6

T19

10

auto[1]

31281

1

T22

4

T54

2

T145

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57746

1

T13

6

T16

6

T19

10

write

3393

1

T56

4

T59

2

T60

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19470

1

T13

2

T16

6

T19

6

valids[0x1]

41669

1

T13

4

T19

4

T20

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1647	1			T64	6		T111	2		T51	1
internal_process_ops[0x5a]	1570	1			T64	6		T60	2		T79	2
internal_process_ops[0x05]	22243	1			T24	4		T64	10		T65	32
internal_process_ops[0x35]	1574	1			T57	2		T105	4		T66	4
internal_process_ops[0x15]	1560	1			T24	2		T64	2		T111	2
internal_process_ops[0x03]	1069	1			T13	2		T19	4		T24	2
internal_process_ops[0x0b]	1099	1			T13	2		T22	1		T24	2
internal_process_ops[0x3b]	1028	1			T19	2		T22	1		T24	4
internal_process_ops[0x6b]	1054	1			T22	2		T24	4		T57	4
internal_process_ops[0xbb]	1107	1			T13	2		T20	2		T56	2
internal_process_ops[0xeb]	1086	1			T19	4		T57	2		T56	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59462

1

T13

6

T16

6

T19

10

auto[1]

1677

1

T66

2

T52

4

T67

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58693

1

T13

6

T16

6

T19

10

auto[1]

2446

1

T65

2

T51

4

T68

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9675

1

T23

16

T24

6

T25

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6205

1

T62

4

T63

6

T67

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2112

1

T13

2

T20

4

T24

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1860

1

T62

2

T66

18

T63

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2440

1

T13

2

T19

6

T20

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2100

1

T62

2

T66

2

T67

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1996

1

T13

2

T19

4

T20

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1862

1

T16

6

T62

10

T66

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T198

2

T199

2

T49

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T67

2

T48

4

T71

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T49

1

T50

1

T200

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T66

2

T48

1

T72

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T56

4

T60

4

T190

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T48

3

T49

1

T50

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T49

1

T70

2

T37

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T67

1

T73

4

T50

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T59

2

T201

2

T49

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T34

1

T49

1

T202

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T48

1

T49

1

T50

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

127

1

T73

4

T50

1

T203

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

121

1

T68

2

T67

1

T48

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T34

1

T36

2

T204

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T48

1

T50

1

T36

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

120

1

T48

2

T74

2

T49

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11698

1

T51

6

T52

25

T53

26

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7834

1

T51

44

T52

8

T53

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1575

1

T22

1

T54

1

T145

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1502

1

T51

1

T52

4

T53

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1912

1

T22

1

T54

1

T51

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1915

1

T51

1

T52

5

T53

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1614

1

T22

2

T145

1

T55

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1446

1

T51

3

T52

5

T53

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T102

3

T103

1

T205

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T102

1

T104

2

T35

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T103

1

T109

4

T206

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T109

1

T114

1

T115

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

147

1

T52

1

T53

2

T102

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T102

2

T104

2

T207

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T109

1

T208

1

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T53

1

T102

1

T109

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

136

1

T53

1

T115

1

T208

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

115

1

T137

4

T209

2

T206

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

124

1

T103

1

T109

2

T115

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

117

1

T53

1

T102

1

T109

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T52

3

T102

1

T109

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

106

1

T52

2

T109

1

T114

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

119

1

T53

3

T102

1

T207

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T52

2

T53

1

T109

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3713	1			T16	6		T23	16		T25	6
auto[0]	values[0]	valids[0x1]	15042	1			T19	4		T20	2		T24	6
auto[0]	values[1]	valids[0x1]	602	1			T66	4		T126	2		T67	3
auto[0]	values[2]	valids[0x0]	556	1			T20	2		T62	4		T67	2
auto[0]	values[2]	valids[0x1]	321	1			T111	4		T67	1		T48	1
auto[0]	values[3]	valids[0x0]	555	1			T19	2		T57	2		T65	2
auto[0]	values[3]	valids[0x1]	265	1			T111	2		T67	1		T210	4
auto[0]	values[4]	valids[0x0]	520	1			T19	4		T57	2		T56	6
auto[0]	values[4]	valids[0x1]	304	1			T49	7		T70	1		T50	2
auto[0]	values[5]	valids[0x0]	538	1			T67	6		T48	4		T71	2
auto[0]	values[5]	valids[0x1]	319	1			T64	6		T67	1		T48	3
auto[0]	values[6]	valids[0x0]	552	1			T57	4		T79	2		T211	2
auto[0]	values[6]	valids[0x1]	284	1			T60	2		T67	1		T48	5
auto[0]	values[7]	valids[0x0]	496	1			T65	2		T105	2		T212	2
auto[0]	values[7]	valids[0x1]	286	1			T67	3		T213	6		T136	2
auto[0]	values[8]	valids[0x0]	3488	1			T13	2		T20	10		T24	8
auto[0]	values[8]	valids[0x1]	2017	1			T13	4		T24	4		T57	2
auto[1]	values[0]	valids[0x0]	4062	1			T51	4		T52	15		T53	17
auto[1]	values[0]	valids[0x1]	18288	1			T22	1		T54	1		T51	46
auto[1]	values[1]	valids[0x1]	624	1			T52	1		T53	9		T102	6
auto[1]	values[2]	valids[0x0]	402	1			T55	2		T51	2		T52	1
auto[1]	values[2]	valids[0x1]	271	1			T53	3		T102	4		T103	2
auto[1]	values[3]	valids[0x0]	348	1			T109	4		T114	3		T137	4
auto[1]	values[3]	valids[0x1]	238	1			T52	4		T102	1		T103	1
auto[1]	values[4]	valids[0x0]	397	1			T52	1		T53	2		T102	3
auto[1]	values[4]	valids[0x1]	248	1			T102	1		T109	9		T115	1
auto[1]	values[5]	valids[0x0]	402	1			T22	3		T145	2		T52	6
auto[1]	values[5]	valids[0x1]	300	1			T53	1		T102	5		T103	1
auto[1]	values[6]	valids[0x0]	397	1			T52	4		T102	1		T103	7
auto[1]	values[6]	valids[0x1]	258	1			T52	1		T53	1		T102	2
auto[1]	values[7]	valids[0x0]	353	1			T145	1		T51	2		T53	1
auto[1]	values[7]	valids[0x1]	206	1			T52	2		T115	4		T214	2
auto[1]	values[8]	valids[0x0]	2691	1			T54	1		T51	5		T52	11
auto[1]	values[8]	valids[0x1]	1796	1			T145	1		T51	4		T52	6