Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3433783

1

T13

709

T16

1

T19

3350

auto[1]

29787

1

T65

30

T51

43

T68

6

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980288

1

T13

709

T16

1

T19

3350

auto[1]

2483282

1

T57

1024

T111

256

T65

3316

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	690284	1			T13	131		T16	1		T19	1262
auto[524288:1048575]	376548	1			T13	80		T19	66		T23	915
auto[1048576:1572863]	432193	1			T19	37		T23	4		T25	801
auto[1572864:2097151]	377621	1			T19	799		T22	68		T23	18
auto[2097152:2621439]	431997	1			T19	106		T23	4		T24	8
auto[2621440:3145727]	358757	1			T13	2		T19	650		T22	4
auto[3145728:3670015]	391963	1			T13	121		T19	40		T24	100
auto[3670016:4194303]	404207	1			T13	375		T19	390		T23	11

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2518367

1

T13

44

T16

1

T19

550

auto[1]

945203

1

T13

665

T19

2800

T22

316

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3051918

1

T13

709

T16

1

T19

3350

auto[1]

411652

1

T23

371

T61

1

T107

27

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	246890	1			T13	131		T16	1		T19	1262
auto[0]	auto[0]	auto[0:524287]	auto[1]	383897	1			T57	1024		T111	124		T65	3288
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	84274	1			T13	80		T19	66		T23	914
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	228474	1			T52	942		T102	1		T103	662
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	99973	1			T19	37		T25	801		T64	185
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	269010	1			T52	257		T102	2246		T103	258
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	106971	1			T19	799		T22	68		T23	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	236362	1			T51	1		T67	1		T53	2233
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	125573	1			T19	106		T24	8		T25	725
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	231795	1			T111	3		T67	385		T102	484
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	104826	1			T13	2		T19	650		T22	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	200584	1			T52	1513		T53	983		T102	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	86298	1			T13	121		T19	40		T24	100
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	269793	1			T111	124		T51	2		T52	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113446	1			T13	375		T19	390		T24	212
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	240810	1			T111	5		T53	320		T103	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	2205	1			T107	2		T52	6		T67	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	53293	1			T67	1		T103	6		T207	395
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	732	1			T23	1		T107	2		T108	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	60001	1			T103	1		T109	257		T115	928
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1472	1			T23	4		T107	21		T53	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58214	1			T48	517		T49	512		T243	200
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	517	1			T23	17		T108	15		T53	19
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	30928	1			T48	512		T115	3		T49	515
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	629	1			T23	4		T107	2		T53	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	70682	1			T48	1818		T109	1		T35	645
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	801	1			T23	334		T61	1		T53	24
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	48435	1			T53	256		T102	1913		T212	2928
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	914	1			T103	4		T48	5		T299	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	29875	1			T103	7		T48	514		T114	329
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	760	1			T23	11		T67	2		T53	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45349	1			T53	1932		T35	513		T203	2593
auto[1]	auto[0]	auto[0:524287]	auto[0]	462	1			T65	2		T51	1		T68	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2631	1			T65	28		T51	3		T68	4
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	402	1			T52	6		T102	6		T104	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1956	1			T104	8		T48	14		T35	58
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	407	1			T102	10		T109	4		T115	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2272	1			T109	11		T115	1		T49	71
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	320	1			T51	1		T52	3		T67	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1709	1			T51	5		T48	9		T109	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	417	1			T52	3		T67	1		T102	28
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2236	1			T67	13		T102	284		T103	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	378	1			T52	3		T53	4		T48	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2058	1			T48	1		T71	19		T208	22
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	428	1			T51	2		T52	2		T53	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4003	1			T51	31		T102	79		T109	52
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	420	1			T53	3		T102	5		T109	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2843	1			T53	64		T109	2		T49	10
auto[1]	auto[1]	auto[0:524287]	auto[0]	106	1			T67	1		T102	8		T49	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	800	1			T49	102		T209	9		T206	43
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	105	1			T103	1		T109	1		T243	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	604	1			T103	14		T109	4		T243	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	105	1			T114	2		T35	4		T50	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	740	1			T35	106		T50	10		T197	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	108	1			T115	1		T49	3		T252	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	706	1			T115	11		T49	91		T252	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	94	1			T53	3		T109	1		T37	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	571	1			T37	6		T197	1		T273	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	71	1			T102	3		T114	11		T50	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1604	1			T53	1		T102	1111		T114	72
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	85	1			T48	2		T114	3		T49	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	567	1			T48	11		T49	60		T243	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T114	9		T35	1		T203	12
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	480	1			T35	27		T273	39		T225	13

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2087794	1			T13	44		T16	1		T19	550
auto[0]	auto[0]	auto[1]	941182	1			T13	665		T19	2800		T22	316
auto[0]	auto[1]	auto[0]	401501	1			T23	15		T61	1		T107	9
auto[0]	auto[1]	auto[1]	3306	1			T23	356		T107	18		T108	2
auto[1]	auto[0]	auto[0]	22369	1			T65	30		T51	40		T68	5
auto[1]	auto[0]	auto[1]	573	1			T51	3		T68	1		T52	5
auto[1]	auto[1]	auto[0]	6703	1			T67	1		T53	3		T102	1120
auto[1]	auto[1]	auto[1]	142	1			T53	1		T102	2		T114	2