Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2378937	1			T1	1		T3	1		T4	1
all_pins[1]	2378937	1			T1	1		T3	1		T4	1
all_pins[2]	2378937	1			T1	1		T3	1		T4	1
all_pins[3]	2378937	1			T1	1		T3	1		T4	1
all_pins[4]	2378937	1			T1	1		T3	1		T4	1
all_pins[5]	2378937	1			T1	1		T3	1		T4	1
all_pins[6]	2378937	1			T1	1		T3	1		T4	1
all_pins[7]	2378937	1			T1	1		T3	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18933324	1			T1	8		T3	8		T4	8
values[0x1]	98172	1			T34	10		T35	482		T36	12
transitions[0x0=>0x1]	96495	1			T34	5		T35	480		T36	12
transitions[0x1=>0x0]	96511	1			T34	5		T35	480		T36	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2378701	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	236	1			T34	1		T35	2		T36	4
all_pins[0]	transitions[0x0=>0x1]	156	1			T36	4		T37	6		T196	2
all_pins[0]	transitions[0x1=>0x0]	197	1			T35	1		T37	2		T196	6
all_pins[1]	values[0x0]	2378660	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	277	1			T34	1		T35	3		T37	3
all_pins[1]	transitions[0x0=>0x1]	196	1			T34	1		T35	3		T37	3
all_pins[1]	transitions[0x1=>0x0]	157	1			T35	3		T36	4		T37	3
all_pins[2]	values[0x0]	2378699	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	238	1			T35	3		T36	4		T37	3
all_pins[2]	transitions[0x0=>0x1]	190	1			T35	3		T36	4		T37	3
all_pins[2]	transitions[0x1=>0x0]	145	1			T34	1		T36	1		T37	4
all_pins[3]	values[0x0]	2378744	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	193	1			T34	1		T36	1		T37	4
all_pins[3]	transitions[0x0=>0x1]	154	1			T34	1		T36	1		T37	3
all_pins[3]	transitions[0x1=>0x0]	137	1			T34	1		T35	2		T36	1
all_pins[4]	values[0x0]	2378761	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	176	1			T34	1		T35	2		T36	1
all_pins[4]	transitions[0x0=>0x1]	134	1			T35	2		T36	1		T37	5
all_pins[4]	transitions[0x1=>0x0]	1610	1			T34	1		T35	2		T36	2
all_pins[5]	values[0x0]	2377285	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	1652	1			T34	2		T35	2		T36	2
all_pins[5]	transitions[0x0=>0x1]	376	1			T35	2		T36	2		T37	3
all_pins[5]	transitions[0x1=>0x0]	93941	1			T34	1		T35	470		T37	7
all_pins[6]	values[0x0]	2283720	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	95217	1			T34	3		T35	470		T37	7
all_pins[6]	transitions[0x0=>0x1]	95170	1			T34	3		T35	470		T37	5
all_pins[6]	transitions[0x1=>0x0]	136	1			T34	1		T37	2		T197	6
all_pins[7]	values[0x0]	2378754	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	183	1			T34	1		T37	4		T196	1
all_pins[7]	transitions[0x0=>0x1]	119	1			T37	2		T197	8		T181	2
all_pins[7]	transitions[0x1=>0x0]	188	1			T35	2		T36	4		T37	6