Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17023

1

T13

6

T19

10

T20

14

auto[1]

12835

1

T16

6

T62

18

T66

26

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3522	1			T16	6		T57	14		T58	4
values[1]	3319	1			T25	6		T64	24		T65	52
values[2]	3719	1			T23	16		T60	18		T62	18
values[3]	3589	1			T13	6		T19	10		T128	12
values[4]	3838	1			T108	20		T66	26		T126	2
values[5]	4630	1			T56	16		T63	10		T79	14
values[6]	3865	1			T24	18		T61	14		T80	2
values[7]	3376	1			T20	14		T111	10		T105	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3259	1			T16	6		T25	6		T64	24
values[1]	4122	1			T24	18		T65	52		T63	10
values[2]	3359	1			T57	14		T111	10		T108	20
values[3]	3257	1			T58	4		T59	14		T62	18
values[4]	4318	1			T60	18		T68	12		T126	2
values[5]	3569	1			T23	16		T56	16		T107	20
values[6]	3875	1			T19	10		T20	14		T105	10
values[7]	4099	1			T13	6		T61	14		T66	26

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	191	1			T202	12		T300	8		T235	12
auto[0]	values[0]	values[1]	251	1			T251	22		T301	18		T302	2
auto[0]	values[0]	values[2]	492	1			T57	14		T213	8		T50	10
auto[0]	values[0]	values[3]	147	1			T58	4		T59	14		T50	16
auto[0]	values[0]	values[4]	289	1			T70	19		T50	12		T237	10
auto[0]	values[0]	values[5]	230	1			T107	20		T203	12		T303	8
auto[0]	values[0]	values[6]	255	1			T48	31		T304	9		T184	14
auto[0]	values[0]	values[7]	247	1			T239	139		T305	14		T306	15
auto[0]	values[1]	values[0]	285	1			T25	6		T64	24		T280	6
auto[0]	values[1]	values[1]	236	1			T65	52		T49	40		T275	18
auto[0]	values[1]	values[2]	193	1			T227	17		T232	13		T306	9
auto[0]	values[1]	values[3]	124	1			T50	18		T227	10		T307	10
auto[0]	values[1]	values[4]	343	1			T50	111		T239	14		T308	16
auto[0]	values[1]	values[5]	289	1			T49	20		T239	12		T253	16
auto[0]	values[1]	values[6]	155	1			T49	23		T202	6		T309	39
auto[0]	values[1]	values[7]	169	1			T67	17		T201	12		T200	12
auto[0]	values[2]	values[0]	247	1			T203	24		T294	22		T310	10
auto[0]	values[2]	values[1]	174	1			T36	20		T233	9		T282	12
auto[0]	values[2]	values[2]	100	1			T133	8		T36	9		T278	11
auto[0]	values[2]	values[3]	277	1			T289	4		T50	17		T36	73
auto[0]	values[2]	values[4]	274	1			T60	18		T68	12		T249	8
auto[0]	values[2]	values[5]	356	1			T23	16		T48	8		T311	8
auto[0]	values[2]	values[6]	275	1			T49	75		T312	4		T313	24
auto[0]	values[2]	values[7]	187	1			T200	7		T202	4		T246	35
auto[0]	values[3]	values[0]	263	1			T48	28		T288	16		T203	13
auto[0]	values[3]	values[1]	301	1			T203	34		T314	18		T227	13
auto[0]	values[3]	values[2]	295	1			T128	12		T36	12		T315	22
auto[0]	values[3]	values[3]	235	1			T34	13		T316	4		T258	13
auto[0]	values[3]	values[4]	152	1			T249	18		T227	8		T232	18
auto[0]	values[3]	values[5]	207	1			T37	13		T227	7		T204	10
auto[0]	values[3]	values[6]	348	1			T19	10		T317	4		T242	141
auto[0]	values[3]	values[7]	250	1			T13	6		T49	11		T318	8
auto[0]	values[4]	values[0]	275	1			T135	4		T37	17		T319	4
auto[0]	values[4]	values[1]	527	1			T50	17		T203	9		T298	69
auto[0]	values[4]	values[2]	161	1			T108	20		T296	20		T282	16
auto[0]	values[4]	values[3]	213	1			T210	4		T199	16		T320	2
auto[0]	values[4]	values[4]	269	1			T126	2		T69	16		T202	13
auto[0]	values[4]	values[5]	197	1			T36	11		T246	13		T267	17
auto[0]	values[4]	values[6]	291	1			T190	10		T49	16		T227	8
auto[0]	values[4]	values[7]	403	1			T67	13		T321	14		T249	10
auto[0]	values[5]	values[0]	294	1			T247	16		T256	10		T305	19
auto[0]	values[5]	values[1]	240	1			T49	9		T203	11		T322	10
auto[0]	values[5]	values[2]	179	1			T34	12		T37	14		T323	6
auto[0]	values[5]	values[3]	445	1			T79	14		T249	11		T240	12
auto[0]	values[5]	values[4]	260	1			T48	12		T259	16		T49	9
auto[0]	values[5]	values[5]	557	1			T56	16		T212	13		T324	6
auto[0]	values[5]	values[6]	265	1			T298	21		T250	13		T204	7
auto[0]	values[5]	values[7]	419	1			T71	13		T70	7		T36	11
auto[0]	values[6]	values[0]	227	1			T49	13		T249	12		T325	4
auto[0]	values[6]	values[1]	215	1			T24	18		T71	11		T326	14
auto[0]	values[6]	values[2]	300	1			T136	10		T50	31		T249	11
auto[0]	values[6]	values[3]	297	1			T327	8		T232	30		T233	9
auto[0]	values[6]	values[4]	347	1			T49	20		T202	10		T304	16
auto[0]	values[6]	values[5]	230	1			T328	8		T203	16		T329	10
auto[0]	values[6]	values[6]	285	1			T198	10		T48	11		T49	11
auto[0]	values[6]	values[7]	391	1			T61	14		T80	2		T50	9
auto[0]	values[7]	values[0]	170	1			T264	14		T249	17		T330	2
auto[0]	values[7]	values[1]	338	1			T67	9		T48	5		T49	11
auto[0]	values[7]	values[2]	151	1			T111	10		T36	22		T255	8
auto[0]	values[7]	values[3]	258	1			T241	10		T331	16		T267	46
auto[0]	values[7]	values[4]	259	1			T132	10		T48	15		T276	14
auto[0]	values[7]	values[5]	144	1			T202	11		T230	18		T332	8
auto[0]	values[7]	values[6]	265	1			T20	14		T105	10		T203	9
auto[0]	values[7]	values[7]	314	1			T131	10		T299	10		T36	8
auto[1]	values[0]	values[0]	202	1			T16	6		T202	8		T235	39
auto[1]	values[0]	values[1]	148	1			T73	26		T256	5		T333	4
auto[1]	values[0]	values[2]	221	1			T50	27		T203	11		T249	7
auto[1]	values[0]	values[3]	99	1			T50	4		T202	11		T282	10
auto[1]	values[0]	values[4]	284	1			T70	6		T50	78		T274	9
auto[1]	values[0]	values[5]	145	1			T211	2		T203	8		T291	8
auto[1]	values[0]	values[6]	219	1			T48	7		T334	24		T304	11
auto[1]	values[0]	values[7]	102	1			T239	11		T305	6		T306	5
auto[1]	values[1]	values[0]	151	1			T50	30		T204	8		T235	11
auto[1]	values[1]	values[1]	170	1			T49	10		T248	8		T335	5
auto[1]	values[1]	values[2]	215	1			T227	3		T232	7		T306	17
auto[1]	values[1]	values[3]	118	1			T50	36		T227	10		T336	8
auto[1]	values[1]	values[4]	161	1			T50	6		T239	6		T200	33
auto[1]	values[1]	values[5]	162	1			T49	11		T239	8		T233	10
auto[1]	values[1]	values[6]	436	1			T49	10		T202	14		T337	4
auto[1]	values[1]	values[7]	112	1			T67	3		T338	2		T200	11
auto[1]	values[2]	values[0]	174	1			T203	16		T282	13		T256	105
auto[1]	values[2]	values[1]	263	1			T36	30		T233	12		T282	8
auto[1]	values[2]	values[2]	239	1			T36	14		T278	9		T266	10
auto[1]	values[2]	values[3]	255	1			T62	18		T50	10		T36	14
auto[1]	values[2]	values[4]	195	1			T72	16		T249	12		T227	9
auto[1]	values[2]	values[5]	224	1			T48	23		T266	10		T332	8
auto[1]	values[2]	values[6]	148	1			T49	7		T246	19		T260	8
auto[1]	values[2]	values[7]	331	1			T75	10		T200	68		T202	132
auto[1]	values[3]	values[0]	83	1			T48	9		T203	7		T175	6
auto[1]	values[3]	values[1]	340	1			T203	26		T227	7		T339	11
auto[1]	values[3]	values[2]	185	1			T36	8		T340	16		T278	10
auto[1]	values[3]	values[3]	142	1			T34	7		T258	14		T336	15
auto[1]	values[3]	values[4]	99	1			T74	16		T249	9		T227	12
auto[1]	values[3]	values[5]	139	1			T37	7		T227	13		T204	10
auto[1]	values[3]	values[6]	183	1			T239	4		T291	49		T233	22
auto[1]	values[3]	values[7]	367	1			T49	9		T204	49		T341	14
auto[1]	values[4]	values[0]	120	1			T37	10		T250	8		T202	5
auto[1]	values[4]	values[1]	190	1			T50	3		T203	11		T298	7
auto[1]	values[4]	values[2]	176	1			T282	4		T266	10		T342	8
auto[1]	values[4]	values[3]	126	1			T37	5		T182	19		T332	23
auto[1]	values[4]	values[4]	230	1			T202	7		T271	8		T254	20
auto[1]	values[4]	values[5]	225	1			T36	21		T246	7		T267	3
auto[1]	values[4]	values[6]	210	1			T49	4		T227	12		T343	7
auto[1]	values[4]	values[7]	225	1			T66	26		T67	22		T344	2
auto[1]	values[5]	values[0]	180	1			T256	10		T305	1		T345	10
auto[1]	values[5]	values[1]	269	1			T63	10		T49	132		T203	9
auto[1]	values[5]	values[2]	137	1			T34	8		T37	8		T298	13
auto[1]	values[5]	values[3]	135	1			T249	17		T290	10		T282	10
auto[1]	values[5]	values[4]	734	1			T48	8		T49	110		T50	144
auto[1]	values[5]	values[5]	173	1			T212	7		T250	8		T227	13
auto[1]	values[5]	values[6]	180	1			T298	10		T250	8		T204	28
auto[1]	values[5]	values[7]	163	1			T71	7		T70	13		T36	9
auto[1]	values[6]	values[0]	263	1			T49	87		T249	8		T346	12
auto[1]	values[6]	values[1]	270	1			T71	30		T202	8		T347	16
auto[1]	values[6]	values[2]	183	1			T50	6		T249	9		T248	13
auto[1]	values[6]	values[3]	151	1			T232	10		T233	29		T175	10
auto[1]	values[6]	values[4]	183	1			T49	9		T202	10		T304	7
auto[1]	values[6]	values[5]	103	1			T203	4		T343	11		T333	12
auto[1]	values[6]	values[6]	219	1			T48	9		T49	9		T110	10
auto[1]	values[6]	values[7]	201	1			T50	18		T348	10		T349	2
auto[1]	values[7]	values[0]	134	1			T249	3		T227	9		T232	13
auto[1]	values[7]	values[1]	190	1			T67	12		T48	15		T49	9
auto[1]	values[7]	values[2]	132	1			T277	4		T36	22		T274	15
auto[1]	values[7]	values[3]	235	1			T350	12		T351	22		T267	8
auto[1]	values[7]	values[4]	239	1			T48	12		T49	78		T110	9
auto[1]	values[7]	values[5]	188	1			T202	34		T332	17		T235	32
auto[1]	values[7]	values[6]	141	1			T203	11		T249	8		T197	6
auto[1]	values[7]	values[7]	218	1			T36	18		T298	9		T336	11