Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	429	1			T13	6		T105	4		T128	4
auto[ReadAddrCrossIntoMailbox]	297	1			T67	1		T48	2		T212	1
auto[ReadAddrCrossOutOfMailbox]	301	1			T71	1		T49	4		T288	4
auto[ReadAddrCrossAllMailbox]	267	1			T19	2		T210	2		T48	1
auto[ReadAddrOutsideMailbox]	3497	1			T19	8		T20	2		T24	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2367

1

T13

3

T19

5

T20

1

auto[1]

2424

1

T13

3

T19

5

T20

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	798	1			T13	2		T19	4		T24	2
read_ops[0x0b]	795	1			T13	2		T24	2		T111	4
read_ops[0x3b]	783	1			T19	2		T24	4		T57	2
read_ops[0x6b]	803	1			T24	4		T57	4		T79	4
read_ops[0xbb]	813	1			T13	2		T20	2		T56	2
read_ops[0xeb]	799	1			T19	4		T57	2		T56	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T13	1		T213	2		T48	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T13	1		T213	2		T212	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T49	1		T50	1		T291	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T67	1		T49	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T246	1		T267	3		T333	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T49	1		T50	1		T203	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T19	1		T210	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T19	1		T210	1		T232	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T19	1		T24	1		T58	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T19	1		T24	1		T58	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T13	1		T272	2		T249	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T13	1		T49	1		T272	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T288	1		T235	1		T260	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T49	1		T288	1		T203	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T49	1		T288	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T49	1		T288	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T249	1		T353	1		T254	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T202	2		T353	1		T246	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T24	1		T111	2		T60	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T24	1		T111	2		T60	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T105	1		T128	1		T49	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T105	1		T128	1		T71	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T48	1		T50	1		T249	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T212	1		T71	1		T50	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T50	1		T249	1		T269	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T50	3		T203	1		T249	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T203	1		T249	1		T298	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T50	1		T203	1		T298	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T19	1		T24	2		T57	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T19	1		T24	2		T57	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T48	1		T212	1		T71	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T135	1		T49	1		T288	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T49	1		T258	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T203	1		T250	1		T353	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T49	1		T50	1		T36	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T50	1		T203	1		T250	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T289	1		T36	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T289	1		T202	1		T353	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T24	2		T57	2		T79	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T24	2		T57	2		T79	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T13	1		T105	1		T288	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T13	1		T105	1		T288	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T289	1		T49	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T289	1		T202	1		T233	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T288	1		T36	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T288	1		T50	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T50	1		T249	1		T265	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T50	2		T249	1		T265	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T20	1		T56	1		T65	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T20	1		T56	1		T65	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T128	1		T212	1		T272	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T128	1		T272	1		T50	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T282	2		T254	1		T235	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T48	1		T36	1		T203	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T71	1		T265	2		T232	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T50	2		T202	1		T265	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T203	1		T287	1		T232	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T48	1		T50	1		T36	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T19	2		T57	1		T56	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T19	2		T57	1		T56	1