Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3082	1			T65	52		T67	35		T136	10
values[1]	3975	1			T23	16		T59	14		T111	10
values[2]	4343	1			T19	10		T64	24		T57	14
values[3]	3639	1			T16	6		T25	6		T68	12
values[4]	3755	1			T60	18		T80	2		T48	38
values[5]	3986	1			T108	20		T126	2		T132	10
values[6]	3650	1			T13	6		T20	14		T61	14
values[7]	3428	1			T24	18		T63	10		T79	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3630	1			T60	18		T63	10		T68	12
values[1]	3679	1			T20	14		T24	18		T57	14
values[2]	3074	1			T58	4		T107	20		T280	6
values[3]	3974	1			T13	6		T64	24		T59	14
values[4]	3546	1			T25	6		T56	16		T72	16
values[5]	4160	1			T111	10		T105	10		T66	26
values[6]	3676	1			T16	6		T23	16		T108	20
values[7]	4119	1			T19	10		T61	14		T67	56

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29060

1

T13

6

T16

6

T19

10

auto[1]

798

1

T66

2

T67

3

T48

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	273	1			T136	10		T48	19		T233	17
auto[0]	values[0]	values[1]	412	1			T65	52		T288	16		T239	20
auto[0]	values[0]	values[2]	366	1			T49	60		T37	22		T197	23
auto[0]	values[0]	values[3]	327	1			T36	65		T203	39		T352	16
auto[0]	values[0]	values[4]	361	1			T135	4		T321	14		T203	20
auto[0]	values[0]	values[5]	318	1			T71	20		T36	26		T250	31
auto[0]	values[0]	values[6]	449	1			T48	27		T50	20		T319	4
auto[0]	values[0]	values[7]	493	1			T67	33		T203	20		T233	23
auto[0]	values[1]	values[0]	547	1			T128	12		T259	16		T283	4
auto[0]	values[1]	values[1]	555	1			T49	20		T316	4		T202	20
auto[0]	values[1]	values[2]	230	1			T204	22		T232	22		T354	10
auto[0]	values[1]	values[3]	561	1			T59	14		T62	18		T48	20
auto[0]	values[1]	values[4]	324	1			T50	27		T202	20		T227	20
auto[0]	values[1]	values[5]	601	1			T111	10		T105	10		T298	76
auto[0]	values[1]	values[6]	548	1			T23	16		T320	2		T50	116
auto[0]	values[1]	values[7]	520	1			T67	20		T212	20		T289	4
auto[0]	values[2]	values[0]	392	1			T67	20		T50	36		T237	10
auto[0]	values[2]	values[1]	240	1			T57	14		T73	18		T355	24
auto[0]	values[2]	values[2]	354	1			T58	4		T107	20		T241	10
auto[0]	values[2]	values[3]	644	1			T64	24		T49	118		T133	8
auto[0]	values[2]	values[4]	598	1			T50	88		T249	27		T353	10
auto[0]	values[2]	values[5]	492	1			T66	24		T49	20		T70	23
auto[0]	values[2]	values[6]	730	1			T210	4		T328	8		T49	93
auto[0]	values[2]	values[7]	789	1			T19	10		T242	141		T239	20
auto[0]	values[3]	values[0]	439	1			T68	12		T211	2		T37	42
auto[0]	values[3]	values[1]	581	1			T296	20		T36	20		T286	12
auto[0]	values[3]	values[2]	370	1			T280	6		T251	22		T255	8
auto[0]	values[3]	values[3]	293	1			T110	20		T327	8		T233	19
auto[0]	values[3]	values[4]	381	1			T25	6		T202	20		T356	2
auto[0]	values[3]	values[5]	874	1			T198	10		T48	17		T49	160
auto[0]	values[3]	values[6]	347	1			T16	6		T36	24		T200	44
auto[0]	values[3]	values[7]	259	1			T357	4		T333	20		T238	16
auto[0]	values[4]	values[0]	691	1			T60	18		T50	37		T36	23
auto[0]	values[4]	values[1]	444	1			T48	35		T298	24		T293	4
auto[0]	values[4]	values[2]	480	1			T344	2		T277	4		T36	20
auto[0]	values[4]	values[3]	372	1			T275	18		T50	47		T36	32
auto[0]	values[4]	values[4]	448	1			T34	19		T36	20		T37	27
auto[0]	values[4]	values[5]	457	1			T80	2		T74	14		T247	16
auto[0]	values[4]	values[6]	288	1			T203	20		T294	22		T233	20
auto[0]	values[4]	values[7]	462	1			T69	16		T258	27		T230	18
auto[0]	values[5]	values[0]	324	1			T50	34		T301	18		T232	20
auto[0]	values[5]	values[1]	505	1			T201	12		T49	82		T50	18
auto[0]	values[5]	values[2]	669	1			T276	14		T37	20		T350	12
auto[0]	values[5]	values[3]	535	1			T126	2		T49	98		T203	18
auto[0]	values[5]	values[4]	422	1			T72	14		T203	19		T249	20
auto[0]	values[5]	values[5]	370	1			T48	28		T203	56		T300	8
auto[0]	values[5]	values[6]	468	1			T108	20		T132	10		T36	18
auto[0]	values[5]	values[7]	598	1			T37	18		T298	31		T339	20
auto[0]	values[6]	values[0]	384	1			T291	60		T314	18		T233	20
auto[0]	values[6]	values[1]	310	1			T20	14		T290	10		T202	21
auto[0]	values[6]	values[2]	298	1			T34	19		T272	8		T358	12
auto[0]	values[6]	values[3]	765	1			T13	6		T71	39		T308	16
auto[0]	values[6]	values[4]	490	1			T56	16		T36	20		T203	20
auto[0]	values[6]	values[5]	496	1			T131	10		T213	8		T199	16
auto[0]	values[6]	values[6]	216	1			T317	4		T70	20		T200	73
auto[0]	values[6]	values[7]	583	1			T61	14		T299	10		T278	16
auto[0]	values[7]	values[0]	476	1			T63	10		T48	37		T312	4
auto[0]	values[7]	values[1]	541	1			T24	18		T79	14		T249	20
auto[0]	values[7]	values[2]	219	1			T268	4		T305	19		T359	22
auto[0]	values[7]	values[3]	389	1			T49	20		T360	4		T361	2
auto[0]	values[7]	values[4]	415	1			T239	17		T249	52		T282	60
auto[0]	values[7]	values[5]	420	1			T249	18		T303	8		T256	75
auto[0]	values[7]	values[6]	542	1			T49	79		T249	20		T227	20
auto[0]	values[7]	values[7]	315	1			T75	4		T362	4		T305	28
auto[1]	values[0]	values[0]	13	1			T48	1		T233	4		T363	4
auto[1]	values[0]	values[1]	11	1			T233	2		T305	1		T364	4
auto[1]	values[0]	values[2]	12	1			T49	2		T197	2		T250	2
auto[1]	values[0]	values[3]	12	1			T36	2		T203	1		T227	2
auto[1]	values[0]	values[4]	7	1			T236	1		T365	2		T366	1
auto[1]	values[0]	values[5]	11	1			T250	1		T227	4		T367	1
auto[1]	values[0]	values[6]	11	1			T368	2		T369	4		T370	1
auto[1]	values[0]	values[7]	6	1			T67	2		T282	1		T371	2
auto[1]	values[1]	values[0]	13	1			T204	1		T256	2		T246	1
auto[1]	values[1]	values[1]	5	1			T256	1		T306	1		T261	1
auto[1]	values[1]	values[2]	9	1			T204	1		T256	4		T372	3
auto[1]	values[1]	values[3]	10	1			T298	3		T232	2		T235	1
auto[1]	values[1]	values[4]	3	1			T41	1		T262	2		-	-
auto[1]	values[1]	values[5]	15	1			T304	1		T343	1		T363	1
auto[1]	values[1]	values[6]	13	1			T50	1		T203	2		T186	3
auto[1]	values[1]	values[7]	21	1			T67	1		T338	2		T336	2
auto[1]	values[2]	values[0]	15	1			T50	1		T204	2		T339	1
auto[1]	values[2]	values[1]	11	1			T73	8		T373	1		T374	2
auto[1]	values[2]	values[2]	9	1			T50	1		T343	1		T372	2
auto[1]	values[2]	values[3]	15	1			T49	1		T227	1		T204	1
auto[1]	values[2]	values[4]	13	1			T50	2		T306	2		T367	1
auto[1]	values[2]	values[5]	16	1			T66	2		T70	2		T202	1
auto[1]	values[2]	values[6]	15	1			T50	1		T202	4		T261	2
auto[1]	values[2]	values[7]	10	1			T235	3		T375	2		T376	4
auto[1]	values[3]	values[0]	12	1			T256	2		T42	1		T377	1
auto[1]	values[3]	values[1]	17	1			T291	1		T256	4		T336	1
auto[1]	values[3]	values[2]	11	1			T202	2		T260	1		T373	3
auto[1]	values[3]	values[3]	5	1			T233	1		T378	3		T379	1
auto[1]	values[3]	values[4]	15	1			T332	2		T186	1		T228	4
auto[1]	values[3]	values[5]	23	1			T48	3		T49	1		T235	4
auto[1]	values[3]	values[6]	3	1			T200	1		T333	2		-	-
auto[1]	values[3]	values[7]	9	1			T380	4		T381	3		T370	1
auto[1]	values[4]	values[0]	20	1			T249	1		T233	3		T333	3
auto[1]	values[4]	values[1]	14	1			T48	3		T274	3		T244	2
auto[1]	values[4]	values[2]	15	1			T175	1		T41	2		T382	2
auto[1]	values[4]	values[3]	3	1			T233	3		-	-		-	-
auto[1]	values[4]	values[4]	14	1			T34	1		T333	3		T383	3
auto[1]	values[4]	values[5]	20	1			T74	2		T305	4		T384	1
auto[1]	values[4]	values[6]	13	1			T266	1		T385	3		T386	2
auto[1]	values[4]	values[7]	14	1			T227	1		T175	3		T282	2
auto[1]	values[5]	values[0]	5	1			T306	2		T387	2		T93	1
auto[1]	values[5]	values[1]	5	1			T50	2		T346	2		T388	1
auto[1]	values[5]	values[2]	18	1			T266	4		T235	1		T335	1
auto[1]	values[5]	values[3]	9	1			T49	2		T203	2		T306	1
auto[1]	values[5]	values[4]	18	1			T72	2		T203	1		T248	5
auto[1]	values[5]	values[5]	18	1			T48	3		T203	4		T389	1
auto[1]	values[5]	values[6]	12	1			T36	2		T239	2		T304	1
auto[1]	values[5]	values[7]	10	1			T37	2		T332	1		T256	2
auto[1]	values[6]	values[0]	10	1			T236	2		T363	1		T372	1
auto[1]	values[6]	values[1]	16	1			T390	2		T391	4		T392	2
auto[1]	values[6]	values[2]	9	1			T34	1		T282	5		T366	1
auto[1]	values[6]	values[3]	13	1			T71	2		T204	1		T182	1
auto[1]	values[6]	values[4]	23	1			T393	2		T394	1		T244	2
auto[1]	values[6]	values[5]	13	1			T332	1		T304	3		T244	1
auto[1]	values[6]	values[6]	6	1			T200	2		T376	1		T378	3
auto[1]	values[6]	values[7]	18	1			T278	4		T182	1		T254	1
auto[1]	values[7]	values[0]	16	1			T304	1		T335	2		T371	1
auto[1]	values[7]	values[1]	12	1			T182	1		T339	1		T304	1
auto[1]	values[7]	values[2]	5	1			T305	1		T395	3		T396	1
auto[1]	values[7]	values[3]	21	1			T235	5		T246	3		T333	1
auto[1]	values[7]	values[4]	14	1			T239	3		T249	1		T282	1
auto[1]	values[7]	values[5]	16	1			T249	2		T246	1		T267	2
auto[1]	values[7]	values[6]	15	1			T49	2		T282	1		T389	1
auto[1]	values[7]	values[7]	12	1			T75	6		T236	1		T262	2