Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	787	1			T34	7		T35	10		T36	7
all_values[1]	787	1			T34	7		T35	10		T36	7
all_values[2]	787	1			T34	7		T35	10		T36	7
all_values[3]	787	1			T34	7		T35	10		T36	7
all_values[4]	787	1			T34	7		T35	10		T36	7
all_values[5]	787	1			T34	7		T35	10		T36	7
all_values[6]	787	1			T34	7		T35	10		T36	7
all_values[7]	787	1			T34	7		T35	10		T36	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3338

1

T34

35

T35

44

T36

29

auto[1]

2958

1

T34

21

T35

36

T36

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2451

1

T34

25

T35

30

T36

19

auto[1]

3845

1

T34

31

T35

50

T36

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3536

1

T34

31

T35

47

T36

33

auto[1]

2760

1

T34

25

T35

33

T36

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	168	1			T34	3		T35	3		T37	3
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T34	2		T35	2		T36	2
all_values[0]	auto[0]	auto[1]	auto[0]	107	1			T34	1		T37	2		T196	3
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T35	1		T36	2		T37	2
all_values[0]	auto[1]	auto[0]	auto[1]	176	1			T35	2		T36	1		T37	6
all_values[0]	auto[1]	auto[1]	auto[1]	169	1			T34	1		T35	2		T36	2
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T34	2		T35	1		T36	1
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T35	2		T36	1		T37	2
all_values[1]	auto[0]	auto[1]	auto[0]	138	1			T34	2		T35	1		T36	2
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T35	1		T37	1		T196	2
all_values[1]	auto[1]	auto[0]	auto[1]	174	1			T34	2		T35	3		T36	2
all_values[1]	auto[1]	auto[1]	auto[1]	171	1			T34	1		T35	2		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T34	2		T35	1		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T35	2		T37	4		T196	1
all_values[2]	auto[0]	auto[1]	auto[0]	140	1			T34	3		T35	1		T36	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T35	3		T36	3		T197	2
all_values[2]	auto[1]	auto[0]	auto[1]	170	1			T34	2		T35	2		T37	3
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T35	1		T36	2		T37	5
all_values[3]	auto[0]	auto[0]	auto[0]	150	1			T34	1		T35	3		T36	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T34	1		T36	2		T37	1
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T35	3		T37	1		T196	2
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T36	1		T37	2		T197	1
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T34	3		T35	3		T36	2
all_values[3]	auto[1]	auto[1]	auto[1]	153	1			T34	2		T35	1		T36	1
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T34	2		T35	2		T37	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T35	1		T36	1		T37	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T34	1		T36	4		T37	2
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T35	2		T37	2		T197	3
all_values[4]	auto[1]	auto[0]	auto[1]	180	1			T34	3		T35	1		T36	1
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T34	1		T35	4		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	214	1			T34	2		T35	4		T36	1
all_values[5]	auto[0]	auto[1]	auto[0]	221	1			T34	2		T35	1		T36	2
all_values[5]	auto[1]	auto[0]	auto[1]	198	1			T34	2		T35	3		T36	4
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T34	1		T35	2		T37	4
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T34	2		T35	3		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T37	1		T196	3		T197	1
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T34	1		T35	3		T36	2
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T34	1		T35	1		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	191	1			T34	2		T35	3		T36	1
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T34	1		T36	2		T37	5
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T36	3		T37	3		T196	6
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T34	2		T35	1		T36	1
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T34	1		T35	4		T37	5
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T35	1		T37	1		T197	3
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T34	2		T35	2		T36	3
all_values[7]	auto[1]	auto[1]	auto[1]	152	1			T34	2		T35	2		T37	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal