Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1871

1

T4

7

T8

3

T11

2

auto[1]

1791

1

T4

3

T8

4

T15

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2054

1

T11

2

T28

1

T43

5

auto[1]

1608

1

T4

10

T8

7

T15

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839

1

T4

10

T8

7

T11

1

auto[1]

823

1

T11

1

T28

1

T43

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	702	1			T4	3		T8	2		T15	1
valid[1]	706	1			T4	1		T15	2		T17	2
valid[2]	738	1			T4	3		T8	2		T11	1
valid[3]	772	1			T4	2		T8	1		T15	1
valid[4]	744	1			T4	1		T8	2		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	128	1			T44	3		T85	1		T78	1
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T4	2		T8	1		T29	2
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T43	1		T45	2		T67	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T4	1		T17	2		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	123	1			T11	1		T45	1		T83	1
auto[0]	auto[0]	valid[2]	auto[1]	162	1			T4	3		T8	1		T29	1
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T45	2		T84	1		T85	1
auto[0]	auto[0]	valid[3]	auto[1]	183	1			T15	1		T27	1		T29	2
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T43	1		T405	1		T48	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T4	1		T8	1		T15	1
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T43	1		T45	2		T85	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T4	1		T8	1		T15	1
auto[0]	auto[1]	valid[1]	auto[0]	110	1			T43	1		T84	1		T85	1
auto[0]	auto[1]	valid[1]	auto[1]	145	1			T15	2		T27	1		T29	3
auto[0]	auto[1]	valid[2]	auto[0]	129	1			T45	2		T85	2		T124	1
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T8	1		T27	2		T123	2
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T44	1		T45	2		T85	1
auto[0]	auto[1]	valid[3]	auto[1]	169	1			T4	2		T8	1		T29	3
auto[0]	auto[1]	valid[4]	auto[0]	128	1			T45	2		T67	1		T405	1
auto[0]	auto[1]	valid[4]	auto[1]	153	1			T8	1		T15	1		T27	1
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T67	1		T405	2		T48	1
auto[1]	auto[0]	valid[1]	auto[0]	91	1			T115	1		T110	1		T205	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T45	1		T405	1		T115	2
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T44	1		T67	1		T405	2
auto[1]	auto[0]	valid[4]	auto[0]	97	1			T11	1		T28	1		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T45	1		T85	1		T124	1
auto[1]	auto[1]	valid[1]	auto[0]	84	1			T85	1		T78	1		T405	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T45	1		T85	1		T109	1
auto[1]	auto[1]	valid[3]	auto[0]	91	1			T85	3		T124	1		T405	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T44	1		T207	2		T34	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal