Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51599

1

T10

9

T11

13

T26

4

auto[1]

16687

1

T4

10

T8

7

T15

64

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49374

1

T4

10

T8

7

T10

2

auto[1]

18912

1

T10

7

T11

7

T26

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35011	1			T4	10		T8	7		T10	5
others[1]	5748	1			T10	1		T11	1		T15	3
others[2]	5825	1			T11	1		T15	7		T29	29
others[3]	6597	1			T15	7		T29	26		T123	31
interest[1]	3724	1			T10	2		T11	1		T15	2
interest[4]	22961	1			T4	10		T8	7		T10	5
interest[64]	11381	1			T10	1		T11	5		T15	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16627	1			T10	1		T11	1		T26	1
auto[0]	auto[0]	others[1]	2792	1			T11	1		T28	1		T43	11
auto[0]	auto[0]	others[2]	2800	1			T11	1		T43	4		T44	20
auto[0]	auto[0]	others[3]	3158	1			T43	10		T44	18		T45	28
auto[0]	auto[0]	interest[1]	1816	1			T11	1		T43	6		T44	14
auto[0]	auto[0]	interest[4]	10913	1			T10	1		T11	1		T28	2
auto[0]	auto[0]	interest[64]	5494	1			T10	1		T11	2		T26	1
auto[0]	auto[1]	others[0]	8709	1			T4	10		T8	7		T15	31
auto[0]	auto[1]	others[1]	1400	1			T15	3		T29	19		T123	22
auto[0]	auto[1]	others[2]	1413	1			T15	7		T29	29		T123	23
auto[0]	auto[1]	others[3]	1624	1			T15	7		T29	26		T123	31
auto[0]	auto[1]	interest[1]	832	1			T15	2		T29	9		T123	14
auto[0]	auto[1]	interest[4]	5699	1			T4	10		T8	7		T15	15
auto[0]	auto[1]	interest[64]	2709	1			T15	14		T29	31		T123	48
auto[1]	auto[0]	others[0]	9675	1			T10	4		T11	4		T26	1
auto[1]	auto[0]	others[1]	1556	1			T10	1		T26	1		T43	3
auto[1]	auto[0]	others[2]	1612	1			T43	4		T44	11		T45	12
auto[1]	auto[0]	others[3]	1815	1			T43	10		T44	8		T45	8
auto[1]	auto[0]	interest[1]	1076	1			T10	2		T43	6		T44	9
auto[1]	auto[0]	interest[4]	6349	1			T10	4		T11	1		T26	1
auto[1]	auto[0]	interest[64]	3178	1			T11	3		T43	9		T44	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal