Unified Coverage Report :: Cond split page

Go back

 LINE       19544
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T20
1	1	Covered	T20,T64,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T65,T84
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T145,T44,T65
1	1	Covered	T54,T145,T44

 LINE       19544
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T62,T52,T67
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T64,T56,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T58,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T5,T19,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T56,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T15,T19,T20

 LINE       19544
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T5,T19,T20

 LINE       19544
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T15,T19,T20

 LINE       19544
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T61,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T64,T61,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T61,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T61,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T64,T58,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T20,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T46

 LINE       19544
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T46,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T61,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T54

 LINE       19544
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T46,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T18
1	1	Covered	T19,T64,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T61
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T61
1	1	Covered	T19,T64,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T61
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T61
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T145,T85,T78
1	1	Covered	T20,T64,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T8,T10
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T10,T11,T26
1	1	Covered	T61,T46,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T15
1	1	Covered	T19,T20,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T8,T15
1	1	Covered	T20,T54,T44

 LINE       19544
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T8,T15
1	1	Covered	T19,T64,T58

 LINE       19544
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T29,T123
1	1	Covered	T19,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T29,T123
1	1	Covered	T19,T20,T64

 LINE       19544
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T15,T64,T56
1	1	Covered	T15,T145,T44

 LINE       19544
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T29,T145
1	1	Covered	T20,T64,T61

 LINE       19544
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T19,T29
1	1	Covered	T19,T58,T56

 LINE       19544
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T15,T19,T64
1	1	Covered	T64,T56,T145

 LINE       19544
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T26,T28
1	1	Covered	T10,T11,T19

 LINE       19544
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T26
1	1	Covered	T19,T20,T64

 LINE       19621
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T140,T146,T147
1	1	1	Covered	T10,T11,T18

 LINE       19636
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T19,T64,T61
1	1	0	Covered	T147,T148,T149
1	1	1	Covered	T34,T35,T36

 LINE       19653
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T19,T64,T61
1	1	0	Covered	T140,T146,T147
1	1	1	Covered	T34,T35,T36

 LINE       19670
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T8,T10
1	0	1	Covered	T5,T38,T15
1	1	0	Covered	T138,T150,T146
1	1	1	Covered	T5,T38,T112

 LINE       19673
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T150,T146
1	1	1	Covered	T13,T16,T18

 LINE       19680
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T19
1	1	0	Covered	T140,T146,T147
1	1	1	Covered	T13,T16,T19

 LINE       19687
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T12
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T12

 LINE       19688
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T18,T19
1	1	0	Covered	T138,T147,T148
1	1	1	Covered	T13,T18,T19

 LINE       19697
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T16,T18
1	1	0	Not Covered
1	1	1	Covered	T23,T25,T61

 LINE       19698
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T140,T147
1	1	1	Covered	T13,T16,T18

 LINE       19701
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T16,T18
1	1	0	Not Covered
1	1	1	Covered	T13,T16,T18

 LINE       19702
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T16,T18
1	1	0	Not Covered
1	1	1	Covered	T13,T16,T18

 LINE       19703
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T150,T147,T148
1	1	1	Covered	T13,T18,T19

 LINE       19710
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T140,T148
1	1	1	Covered	T13,T16,T18

 LINE       19715
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T138,T147,T148
1	1	1	Covered	T13,T16,T18

 LINE       19720
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T140,T150,T147
1	1	1	Covered	T13,T16,T18

 LINE       19723
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T140,T146
1	1	1	Covered	T13,T16,T18

 LINE       19726
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T54,T145,T44
1	1	0	Not Covered
1	1	1	Covered	T65,T51,T68

 LINE       19727
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T64,T61
1	1	0	Not Covered
1	1	1	Covered	T65,T68,T52

 LINE       19728
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T150,T146
1	1	1	Covered	T13,T16,T18

 LINE       19793
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T140,T148,T149
1	1	1	Covered	T13,T16,T18

 LINE       19858
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T140,T147,T148
1	1	1	Covered	T13,T16,T18

 LINE       19923
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T147,T148,T149
1	1	1	Covered	T13,T16,T18

 LINE       19988
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T140,T150
1	1	1	Covered	T13,T16,T18

 LINE       20053
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T150,T141
1	1	1	Covered	T13,T16,T18

 LINE       20118
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T140,T146
1	1	1	Covered	T13,T16,T18

 LINE       20183
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T5,T13,T16
1	1	0	Covered	T146,T147,T148
1	1	1	Covered	T13,T16,T18

 LINE       20248
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T139,T150
1	1	1	Covered	T13,T16,T18

 LINE       20251
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T138,T146,T147
1	1	1	Covered	T13,T16,T18

 LINE       20254
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T138,T140,T148
1	1	1	Covered	T13,T16,T18

 LINE       20257
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T5,T13,T16
1	1	0	Covered	T146,T148,T151
1	1	1	Covered	T13,T16,T18

 LINE       20260
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T15,T16
1	1	0	Covered	T138,T146,T147
1	1	1	Covered	T13,T16,T18

 LINE       20287
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T8
1	0	1	Covered	T13,T16,T18
1	1	0	Covered	T140,T148,T152
1	1	1	Covered	T13,T16,T18