Module Definition
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Module : spid_fifo2sram_adapter
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.87 100.00 79.49 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spi_tpm.u_tpm_rd_buffer 93.94 100.00 81.82 100.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer 97.92 100.00 91.67 100.00 100.00
tb.dut.u_upload.u_payload_buffer 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.94 100.00 81.82 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.94 100.00 81.82 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.34 99.29 93.36 91.67 97.40 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.34 99.29 93.36 91.67 97.40 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_upload.u_payload_buffer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.52 100.00 96.88 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_upload.u_payload_buffer

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7311100.00
ALWAYS7666100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9755100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T6 T9 T10 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T6 T9 T10 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T20 T60 T50 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :
SCORELINE
97.92 100.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7311100.00
ALWAYS7666100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9755100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T3 T5 T13 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T3 T5 T13 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T29 T22 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Line Coverage for Module self-instances :
SCORELINE
93.94 100.00
tb.dut.u_spi_tpm.u_tpm_rd_buffer

Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9766100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
74                      
75                          always_comb begin
76                            sram_wdata_o = '0;
77                            sram_wmask_o = '0;
78                            for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
79                              if (fifoptr[0+:SubWordW] == i) begin
80                                sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
81                                sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                              end
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
           Tests:       T1 T2 T3 
88         1/1              assign sram_wdata_o = SramDw'(wdata_i);
           Tests:       T1 T2 T3 
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T5 T14 T29 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
100        1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T5 T14 T29 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T14 T29 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_upload.u_payload_buffer

TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT20,T60,T50 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT20,T60,T50 

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT20,T60,T50 

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT20,T60,T50
1CoveredT20,T50,T62 

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT20,T60,T50
1CoveredT20,T50,T62
Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :
SCORECOND
97.92 91.67
tb.dut.u_spi_tpm.u_tpm_wr_buffer

TotalCoveredPercent
Conditions131184.62
Logical131184.62
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT5,T29,T22 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT5,T29,T22 

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T29,T22 

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT5,T29,T22
1CoveredT5,T22,T30 

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT5,T29,T22
1CoveredT5,T22,T30
Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Cond Coverage for Module self-instances :
SCORECOND
93.94 81.82
tb.dut.u_spi_tpm.u_tpm_rd_buffer

TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT5,T14,T29
10Not Covered
11CoveredT5,T14,T29 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTests
01CoveredT5,T14,T29
10Not Covered
11CoveredT5,T14,T29 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T14,T29 

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT5,T14,T29
1CoveredT14,T22,T30 

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT5,T14,T29
1CoveredT14,T22,T30
Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_upload.u_payload_buffer

Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 97 4 4 100.00
IF 79 2 2 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 1 Covered T20,T50,T62
0 0 1 0 Covered T20,T60,T50
0 0 0 - Covered T6,T9,T10 



79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.92 100.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer

Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 97 4 4 100.00
IF 79 2 2 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 1 Covered T5,T22,T30
0 0 1 0 Covered T5,T29,T22
0 0 0 - Covered T3,T5,T13 



79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
93.94 100.00
tb.dut.u_spi_tpm.u_tpm_rd_buffer

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 97 5 5 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==>
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 1 Covered T14,T22,T30
0 0 1 0 Covered T5,T14,T29
0 0 0 - Covered T5,T14,T29

Assert Coverage for Module : spid_fifo2sram_adapter
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 1952 1952 0 0
g_multiple_entry_per_word.WidthDivideSramDw_A 1952 1952 0 0


g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1952 1952 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

g_multiple_entry_per_word.WidthDivideSramDw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1952 1952 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9766100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
74                      
75                          always_comb begin
76                            sram_wdata_o = '0;
77                            sram_wmask_o = '0;
78                            for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
79                              if (fifoptr[0+:SubWordW] == i) begin
80                                sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
81                                sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                              end
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
           Tests:       T1 T2 T3 
88         1/1              assign sram_wdata_o = SramDw'(wdata_i);
           Tests:       T1 T2 T3 
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T5 T14 T29 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
100        1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T5 T14 T29 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T14 T29 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer
TotalCoveredPercent
Conditions11981.82
Logical11981.82
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT5,T14,T29
10Not Covered
11CoveredT5,T14,T29 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTestsExclude Annotation
01CoveredT5,T14,T29
10Excluded VC_COV_UNR
11CoveredT5,T14,T29 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT5,T14,T29 

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT5,T14,T29
1CoveredT14,T22,T30 

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT5,T14,T29
1CoveredT14,T22,T30
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 97 5 5 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==>
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 1 Covered T14,T22,T30
0 0 1 0 Covered T5,T14,T29
0 0 0 - Covered T5,T14,T29

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7311100.00
ALWAYS7666100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9755100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T3 T5 T13 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T3 T5 T13 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T29 T22 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT5,T29,T22 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT5,T29,T22 

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11CoveredT5,T29,T22 

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT5,T29,T22
1CoveredT5,T22,T30 

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT5,T29,T22
1CoveredT5,T22,T30
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 97 4 4 100.00
IF 79 2 2 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 1 Covered T5,T22,T30
0 0 1 0 Covered T5,T29,T22
0 0 0 - Covered T3,T5,T13 



79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 976 976 0 0
g_multiple_entry_per_word.WidthDivideSramDw_A 976 976 0 0


g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

g_multiple_entry_per_word.WidthDivideSramDw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_upload.u_payload_buffer
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7311100.00
ALWAYS7666100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9411100.00
ALWAYS9755100.00


51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T6 T9 T10 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T6 T9 T10 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T20 T60 T50 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_upload.u_payload_buffer
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT20,T60,T50 

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT20,T60,T50 

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT20,T60,T50 

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------
-1-StatusTests
0CoveredT20,T60,T50
1CoveredT20,T50,T62 

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------
-1-StatusTests
0CoveredT20,T60,T50
1CoveredT20,T50,T62
Branch Coverage for Instance : tb.dut.u_upload.u_payload_buffer
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 97 4 4 100.00
IF 79 2 2 100.00 



97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 1 Covered T20,T50,T62
0 0 1 0 Covered T20,T60,T50
0 0 0 - Covered T6,T9,T10 



79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_upload.u_payload_buffer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 976 976 0 0
g_multiple_entry_per_word.WidthDivideSramDw_A 976 976 0 0


g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

g_multiple_entry_per_word.WidthDivideSramDw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%