e283afb2de283afb2d| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |
| V2 | performance | spi_host_performance | 46 | 50 | 92.00 |
| V2 | error_event_intr | spi_host_error_txrx | 0 | 0 | -- |
| spi_host_error_cmd | 0 | 0 | -- | ||
| spi_host_event | 0 | 0 | -- | ||
| V2 | clock_rate | spi_host_speed | 20 | 50 | 40.00 |
| V2 | speed | spi_host_speed | 20 | 50 | 40.00 |
| V2 | chip_select_timing | spi_host_speed | 20 | 50 | 40.00 |
| V2 | sw_reset | spi_host_sw_reset | 25 | 50 | 50.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 0 | -- |
| V2 | cpol_cpha | spi_host_speed | 20 | 50 | 40.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | endian | endian | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 0 | 0 | -- |
| V2 | winbond | winbond | 0 | 0 | -- |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 231 | 290 | 79.66 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| TOTAL | 341 | 425 | 80.24 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 15 | 7 | 4 | 26.67 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.83 | 87.27 | 80.99 | 88.25 | 78.13 | 93.43 | 70.83 | 97.19 | 89.24 |
UVM_FATAL (spi_host_scoreboard.sv:98) scoreboard [scoreboard] has 27 failures:
3.spi_host_speed.2322821298
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/out/run.log
UVM_FATAL @ 400758729 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
4.spi_host_speed.3458935978
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/out/run.log
UVM_FATAL @ 21937761 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
... and 8 more failures.
4.spi_host_sw_reset.2268685966
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_sw_reset/out/run.log
UVM_FATAL @ 3388640 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
6.spi_host_sw_reset.2479033507
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/out/run.log
UVM_FATAL @ 10009260 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
... and 15 more failures.
UVM_FATAL (spi_host_scoreboard.sv:143) scoreboard [scoreboard] has 9 failures:
1.spi_host_speed.4116346265
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/out/run.log
UVM_FATAL @ 51748328 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] f f
2.spi_host_speed.1448829322
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_speed/out/run.log
UVM_FATAL @ 6172798 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] f0 f0
... and 5 more failures.
1.spi_host_sw_reset.2052453774
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/out/run.log
UVM_FATAL @ 42616080 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 8
byte actual expected
[ 0] 30 30
10.spi_host_sw_reset.1387218056
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/out/run.log
UVM_FATAL @ 138685587 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] fd fd
UVM_FATAL (spi_host_scoreboard.sv:135) scoreboard [scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING * has 7 failures:
0.spi_host_speed.4022268728
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/out/run.log
UVM_FATAL @ 30259622 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 3
UVM_INFO @ 30259622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_speed.6249452
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_speed/out/run.log
UVM_FATAL @ 15479701 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 3
UVM_INFO @ 15479701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
5.spi_host_sw_reset.1249568660
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/out/run.log
UVM_FATAL @ 136585837 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 136585837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_sw_reset.186520568
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/out/run.log
UVM_FATAL @ 83265177 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 83265177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:135) scoreboard [scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING * has 5 failures:
12.spi_host_speed.2507064174
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/out/run.log
UVM_FATAL @ 27342556 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 7
UVM_INFO @ 27342556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_speed.3750557725
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/out/run.log
UVM_FATAL @ 21425631 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 21425631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
20.spi_host_sw_reset.443953900
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/out/run.log
UVM_FATAL @ 4677516 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 4677516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_host_sw_reset.2666224587
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/out/run.log
UVM_FATAL @ 168077517 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 168077517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:143) scoreboard [scoreboard] has 3 failures:
Test spi_host_speed has 2 failures.
6.spi_host_speed.309873466
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/out/run.log
UVM_FATAL @ 16266816 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] f0 f0
13.spi_host_speed.1134332606
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_speed/out/run.log
UVM_FATAL @ 27832360 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] c c
Test spi_host_sw_reset has 1 failures.
28.spi_host_sw_reset.652578096
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/out/run.log
UVM_FATAL @ 23689164 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 6
byte actual expected
[ 0] 1d 1d
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
9.spi_host_performance.1859408835
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_performance/out/run.log
UVM_FATAL @ 10054703278 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x85a0b554) == 0x1
UVM_INFO @ 10054703278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_performance.3619229072
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_performance/out/run.log
UVM_FATAL @ 10199920220 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd724a154) == 0x1
UVM_INFO @ 10199920220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 2 failures:
Test spi_host_performance has 1 failures.
30.spi_host_performance.3315464015
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_performance/out/run.log
UVM_FATAL @ 10147147645 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x5d3ebd94) == 0x0
UVM_INFO @ 10147147645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
33.spi_host_speed.1426938312
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_speed/out/run.log
UVM_FATAL @ 10100815923 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xe7f02c54) == 0x0
UVM_INFO @ 10100815923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 2 failures:
34.spi_host_speed.189494247
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_speed/out/run.log
UVM_FATAL @ 10082741176 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x8965b714) == 0x0
UVM_INFO @ 10082741176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_speed.2623698551
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_speed/out/run.log
UVM_FATAL @ 10119790835 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x60b1f454) == 0x0
UVM_INFO @ 10119790835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10798) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_mem_partial_access.271790448
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1120737 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10798) { a_addr: 'haa7a982b a_data: 'h5d7978f4 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'haa a_opcode: 'h0 a_user: 'h26094 d_param: 'h0 d_source: 'haa d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1120737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11310) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_csr_mem_rw_with_rand_reset.1254240627
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1870172 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11310) { a_addr: 'ha2423e2a a_data: 'h82415f21 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hfa a_opcode: 'h1 a_user: 'h24d8b d_param: 'h0 d_source: 'hfa d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1870172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10943) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_mem_partial_access.2133634397
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 9033088 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10943) { a_addr: 'hdc4cf62a a_data: 'h8f119b91 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h70 a_opcode: 'h1 a_user: 'h275b5 d_param: 'h0 d_source: 'h70 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 9033088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15080) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_csr_mem_rw_with_rand_reset.2069536732
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2187444 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15080) { a_addr: 'h8826682a a_data: 'hd19a3b0a a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h2b a_opcode: 'h1 a_user: 'h249a1 d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2187444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10587) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_mem_partial_access.2028843000
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1502993 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10587) { a_addr: 'hfefcceeb a_data: 'h9e303e67 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h1b a_opcode: 'h0 a_user: 'h259a7 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1502993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14820) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_csr_mem_rw_with_rand_reset.1954524353
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 846551 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14820) { a_addr: 'h9bf6606a a_data: 'hcebc215e a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hfc a_opcode: 'h1 a_user: 'h25b80 d_param: 'h0 d_source: 'hfc d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 846551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12223) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_mem_partial_access.2225785765
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 980238 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12223) { a_addr: 'h1f74bc6a a_data: 'hb95dde0d a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h1e a_opcode: 'h0 a_user: 'h257f2 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 980238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11767) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_csr_mem_rw_with_rand_reset.4070309689
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2804264 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11767) { a_addr: 'ha62d64ea a_data: 'ha5d026e1 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h9c a_opcode: 'h0 a_user: 'h261f0 d_param: 'h0 d_source: 'h9c d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2804264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10564) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_mem_partial_access.1616777153
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 4901741 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10564) { a_addr: 'hb5112f6b a_data: 'h2e95f4b3 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hb2 a_opcode: 'h0 a_user: 'h25bd4 d_param: 'h0 d_source: 'hb2 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4901741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_csr_mem_rw_with_rand_reset.3822913136
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1705827 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11274) { a_addr: 'h8fd3f66b a_data: 'h722c069a a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hb1 a_opcode: 'h0 a_user: 'h26b86 d_param: 'h0 d_source: 'hb1 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1705827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14991) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.spi_host_csr_mem_rw_with_rand_reset.3922828123
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2096863 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14991) { a_addr: 'h836ef56b a_data: 'habb09f34 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h8c a_opcode: 'h0 a_user: 'h254f7 d_param: 'h0 d_source: 'h8c d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2096863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11293) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.spi_host_csr_mem_rw_with_rand_reset.2863824494
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4276554 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11293) { a_addr: 'h74f54429 a_data: 'h89eeafd7 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hc0 a_opcode: 'h0 a_user: 'h276ad d_param: 'h0 d_source: 'hc0 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4276554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11008) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.spi_host_csr_mem_rw_with_rand_reset.930399858
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1287401 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11008) { a_addr: 'ha34f712a a_data: 'hc6e7277b a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hac a_opcode: 'h1 a_user: 'h26879 d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1287401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11369) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.spi_host_csr_mem_rw_with_rand_reset.73236806
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4223787 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11369) { a_addr: 'h125bf9aa a_data: 'h3e922d31 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'hcb a_opcode: 'h1 a_user: 'h24d42 d_param: 'h0 d_source: 'hcb d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4223787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14864) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.spi_host_csr_mem_rw_with_rand_reset.3116343957
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3074187 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14864) { a_addr: 'haa6d7929 a_data: 'hf715953a a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h2 a_opcode: 'h1 a_user: 'h26c5b d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3074187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14954) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.spi_host_csr_mem_rw_with_rand_reset.2902445844
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3141554 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14954) { a_addr: 'h4572096a a_data: 'he9b0b9ed a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'he1 a_opcode: 'h0 a_user: 'h241e3 d_param: 'h0 d_source: 'he1 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3141554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11067) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.spi_host_csr_mem_rw_with_rand_reset.2744733251
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4017906 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11067) { a_addr: 'h17a2656a a_data: 'h4c3f1b1e a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h77 a_opcode: 'h0 a_user: 'h26a1b d_param: 'h0 d_source: 'h77 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4017906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13168) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
12.spi_host_csr_mem_rw_with_rand_reset.3904831802
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1022465 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13168) { a_addr: 'h1013bfa9 a_data: 'h2b91ae19 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hd2 a_opcode: 'h0 a_user: 'h2744b d_param: 'h0 d_source: 'hd2 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1022465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13439) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.spi_host_csr_mem_rw_with_rand_reset.3288398703
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1254902 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13439) { a_addr: 'ha844a2a9 a_data: 'hcfbca322 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hf4 a_opcode: 'h0 a_user: 'h26fe3 d_param: 'h0 d_source: 'hf4 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1254902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11625) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.spi_host_csr_mem_rw_with_rand_reset.1674554269
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1187625 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11625) { a_addr: 'heda28a2a a_data: 'he02e12f3 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h35 a_opcode: 'h0 a_user: 'h2760c d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1187625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11087) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.spi_host_csr_mem_rw_with_rand_reset.633966047
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 6054278 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11087) { a_addr: 'h2d0d19a9 a_data: 'h1a80aced a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hf1 a_opcode: 'h1 a_user: 'h246ee d_param: 'h0 d_source: 'hf1 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 6054278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13525) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.spi_host_csr_mem_rw_with_rand_reset.3358457256
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 969243 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13525) { a_addr: 'h8acca72b a_data: 'h4c725bff a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h11 a_opcode: 'h0 a_user: 'h26276 d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 969243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11287) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.spi_host_csr_mem_rw_with_rand_reset.292225758
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1141983 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11287) { a_addr: 'h9c4136a a_data: 'hb006831 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h2e a_opcode: 'h1 a_user: 'h24e35 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1141983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11324) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.spi_host_csr_mem_rw_with_rand_reset.3972092597
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1565532 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11324) { a_addr: 'h43ce6dea a_data: 'hab1b1efc a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h7 a_opcode: 'h0 a_user: 'h25c6a d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1565532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11563) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.spi_host_csr_mem_rw_with_rand_reset.2556587719
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 9160428 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11563) { a_addr: 'ha7d617ea a_data: 'hf531ad7e a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h3c a_opcode: 'h1 a_user: 'h256c5 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 9160428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:132) scoreboard [scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION has 1 failures:
27.spi_host_speed.1648120307
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_speed/out/run.log
UVM_FATAL @ 42561740 ps: (spi_host_scoreboard.sv:132) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION
UVM_INFO @ 42561740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---