SPI_HOST Simulation Results

Friday May 06 2022 08:04:28 UTC

GitHub Revision: 7cddd1c0e
Foundry Revision: 7cddd1c0e

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 4082396206

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke spi_host_smoke 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 5 5 100.00
V1 csr_rw spi_host_csr_rw 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
V1 TOTAL 85 105 80.95
V2 performance spi_host_performance 45 50 90.00
V2 error_event_intr spi_host_error_txrx 0 0 --
spi_host_error_cmd 0 0 --
spi_host_event 0 0 --
V2 clock_rate spi_host_speed 20 50 40.00
V2 speed spi_host_speed 20 50 40.00
V2 chip_select_timing spi_host_speed 20 50 40.00
V2 sw_reset spi_host_sw_reset 26 50 52.00
V2 passthrough_mode spi_host_passthrough_mode 0 0 --
V2 cpol_cpha spi_host_speed 20 50 40.00
V2 full_cycle full_cycle 0 0 --
V2 endian endian 0 0 --
V2 duplex spi_host_smoke 50 50 100.00
V2 tx_rx_only spi_host_smoke 50 50 100.00
V2 stress_all spi_host_stress_all 0 0 --
V2 winbond winbond 0 0 --
V2 alert_test spi_host_alert_test 50 50 100.00
V2 intr_test spi_host_intr_test 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 5 5 100.00
spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
spi_host_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 5 5 100.00
spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
spi_host_same_csr_outstanding 20 20 100.00
V2 TOTAL 231 290 79.66
V2S tl_intg_err spi_host_tl_intg_err 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_mem_walk 5 5 100.00
spi_host_mem_partial_access 0 5 0.00
TOTAL 341 425 80.24

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 1 50.00
V1 6 6 5 83.33
V2 15 7 4 26.67
V2S 2 1 1 50.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
77.40 87.26 80.99 88.24 78.21 68.90 70.83 97.19 90.79

Failure Buckets

Past Results