c7e620218c7e620218| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |
| V2 | performance | spi_host_performance | 47 | 50 | 94.00 |
| V2 | error_event_intr | spi_host_error_txrx | 0 | 0 | -- |
| spi_host_error_cmd | 0 | 0 | -- | ||
| spi_host_event | 0 | 0 | -- | ||
| V2 | clock_rate | spi_host_speed | 26 | 50 | 52.00 |
| V2 | speed | spi_host_speed | 26 | 50 | 52.00 |
| V2 | chip_select_timing | spi_host_speed | 26 | 50 | 52.00 |
| V2 | sw_reset | spi_host_sw_reset | 17 | 50 | 34.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 0 | -- |
| V2 | cpol_cpha | spi_host_speed | 26 | 50 | 52.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | endian | endian | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 0 | 0 | -- |
| V2 | winbond | winbond | 0 | 0 | -- |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 230 | 290 | 79.31 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| TOTAL | 340 | 425 | 80.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 15 | 7 | 4 | 26.67 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 80.69 | 96.48 | 91.74 | 98.49 | 81.49 | 69.01 | 70.83 | 97.19 | 90.79 |
UVM_FATAL (spi_host_scoreboard.sv:98) scoreboard [scoreboard] has 28 failures:
0.spi_host_sw_reset.2716385445
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/out/run.log
UVM_FATAL @ 9372484 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
1.spi_host_sw_reset.457179732
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/out/run.log
UVM_FATAL @ 77209672 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
... and 19 more failures.
6.spi_host_speed.2356578294
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/out/run.log
UVM_FATAL @ 45348454 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
10.spi_host_speed.2465109820
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_speed/out/run.log
UVM_FATAL @ 10927051 ps: (spi_host_scoreboard.sv:98) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
READ: SPI bus data 0 did not match TL data ff
len 1
byte SPI Bus TL Bus
[0] ff ff
... and 5 more failures.
UVM_FATAL (spi_host_scoreboard.sv:135) scoreboard [scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING * has 10 failures:
1.spi_host_speed.2562881123
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/out/run.log
UVM_FATAL @ 39189889 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 5
UVM_INFO @ 39189889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_speed.1976213211
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/out/run.log
UVM_FATAL @ 20881473 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 20881473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
3.spi_host_sw_reset.2211546221
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/out/run.log
UVM_FATAL @ 40267272 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 40267272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_sw_reset.3463592400
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/out/run.log
UVM_FATAL @ 20853389 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 20853389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (spi_host_scoreboard.sv:143) scoreboard [scoreboard] has 8 failures:
2.spi_host_speed.1484665893
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_speed/out/run.log
UVM_FATAL @ 39344928 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 4
byte actual expected
[ 0] 3 3
8.spi_host_speed.554624684
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/out/run.log
UVM_FATAL @ 4784300 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 10
byte actual expected
[ 0] ce d7
... and 5 more failures.
27.spi_host_sw_reset.2225416142
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_sw_reset/out/run.log
UVM_FATAL @ 113613293 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 16
byte actual expected
[ 0] 29 29
Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:135) scoreboard [scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING * has 6 failures:
11.spi_host_sw_reset.4292737300
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/out/run.log
UVM_FATAL @ 52574833 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 52574833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_sw_reset.949918686
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/out/run.log
UVM_FATAL @ 21698696 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 1
UVM_INFO @ 21698696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
42.spi_host_speed.658427413
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_speed/out/run.log
UVM_FATAL @ 50921082 ps: (spi_host_scoreboard.sv:135) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST BYTE SET PREMATURELY - STILL MISSING 3
UVM_INFO @ 50921082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 4 failures:
Test spi_host_speed has 2 failures.
15.spi_host_speed.1841913926
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_speed/out/run.log
UVM_FATAL @ 10098129421 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xb5ef9294) == 0x0
UVM_INFO @ 10098129421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_speed.2622597019
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_speed/out/run.log
UVM_FATAL @ 10175962168 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x29d96d54) == 0x0
UVM_INFO @ 10175962168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_performance has 2 failures.
19.spi_host_performance.1107957277
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_performance/out/run.log
UVM_FATAL @ 10221898050 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xbff69594) == 0x0
UVM_INFO @ 10221898050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_performance.4079781196
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_performance/out/run.log
UVM_FATAL @ 10135970869 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x30001794) == 0x0
UVM_INFO @ 10135970869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10564) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:
0.spi_host_mem_partial_access.2350308734
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1678624 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10564) { a_addr: 'h3c04a72b a_data: 'h86e1faae a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hf5 a_opcode: 'h1 a_user: 'h2567a d_param: 'h0 d_source: 'hf5 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1678624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_mem_partial_access.2314339695
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 712380 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10564) { a_addr: 'h2337c56b a_data: 'ha4f5cee8 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h63 a_opcode: 'h0 a_user: 'h27395 d_param: 'h0 d_source: 'h63 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 712380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14797) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_csr_mem_rw_with_rand_reset.1798887469
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1317200 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14797) { a_addr: 'hf61842aa a_data: 'h4ff09174 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hc3 a_opcode: 'h1 a_user: 'h2471f d_param: 'h0 d_source: 'hc3 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1317200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13680) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_mem_partial_access.3448063069
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1130665 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13680) { a_addr: 'h39dacb6a a_data: 'h705b9ee0 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'ha8 a_opcode: 'h1 a_user: 'h24281 d_param: 'h0 d_source: 'ha8 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1130665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11329) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_csr_mem_rw_with_rand_reset.3011656578
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1100169 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11329) { a_addr: 'hfb79de2b a_data: 'h7e065291 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h64 a_opcode: 'h0 a_user: 'h271ed d_param: 'h0 d_source: 'h64 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1100169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10714) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_mem_partial_access.3983529077
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2358659 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10714) { a_addr: 'hc00acaa a_data: 'h689f0508 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h8b a_opcode: 'h0 a_user: 'h2652f d_param: 'h0 d_source: 'h8b d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2358659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15077) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_csr_mem_rw_with_rand_reset.3507722055
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3848953 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15077) { a_addr: 'hca87eeb a_data: 'he68ef1bd a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h2a a_opcode: 'h0 a_user: 'h25288 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3848953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10582) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_mem_partial_access.4244010709
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2270457 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10582) { a_addr: 'hb4025f29 a_data: 'hf938f528 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h94 a_opcode: 'h1 a_user: 'h27e8f d_param: 'h0 d_source: 'h94 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2270457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11328) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_csr_mem_rw_with_rand_reset.2718622071
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3169324 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11328) { a_addr: 'hc97bf56b a_data: 'hd4a5911 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h4d a_opcode: 'h1 a_user: 'h247e8 d_param: 'h0 d_source: 'h4d d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3169324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11220) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_csr_mem_rw_with_rand_reset.3854871371
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1119281 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11220) { a_addr: 'hd0e0786a a_data: 'h3dcad3b5 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h48 a_opcode: 'h1 a_user: 'h252b3 d_param: 'h0 d_source: 'h48 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1119281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14910) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.spi_host_csr_mem_rw_with_rand_reset.2296566128
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1124363 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14910) { a_addr: 'h1ae06eab a_data: 'h81d33093 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h9d a_opcode: 'h0 a_user: 'h25cbc d_param: 'h0 d_source: 'h9d d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1124363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13594) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.spi_host_csr_mem_rw_with_rand_reset.681434868
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4962748 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13594) { a_addr: 'he1c64f6a a_data: 'h33c661f1 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h16 a_opcode: 'h1 a_user: 'h26cf6 d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4962748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13392) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.spi_host_csr_mem_rw_with_rand_reset.169774039
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4413543 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13392) { a_addr: 'hfac45f6a a_data: 'hed2d14c0 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'ha4 a_opcode: 'h1 a_user: 'h25ec5 d_param: 'h0 d_source: 'ha4 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4413543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13412) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.spi_host_csr_mem_rw_with_rand_reset.1707793360
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5340334 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13412) { a_addr: 'hd212232a a_data: 'h9e74eeed a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h90 a_opcode: 'h1 a_user: 'h25c60 d_param: 'h0 d_source: 'h90 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5340334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11929) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.spi_host_csr_mem_rw_with_rand_reset.2059269853
Line 55, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 14513517 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11929) { a_addr: 'h8d5333eb a_data: 'h1e2b8126 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h66 a_opcode: 'h0 a_user: 'h26d6f d_param: 'h0 d_source: 'h66 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 14513517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11410) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.spi_host_csr_mem_rw_with_rand_reset.1189624203
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5902045 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11410) { a_addr: 'had25246b a_data: 'h50b79949 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hfa a_opcode: 'h0 a_user: 'h27127 d_param: 'h0 d_source: 'hfa d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5902045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11848) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.spi_host_csr_mem_rw_with_rand_reset.4198996040
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1344384 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11848) { a_addr: 'hd5bbf16b a_data: 'ha8341899 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h98 a_opcode: 'h0 a_user: 'h26ef9 d_param: 'h0 d_source: 'h98 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1344384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15138) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
12.spi_host_csr_mem_rw_with_rand_reset.3687494828
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2013538 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15138) { a_addr: 'h321812aa a_data: 'hcb0a6e12 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hd2 a_opcode: 'h0 a_user: 'h246f5 d_param: 'h0 d_source: 'hd2 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2013538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13584) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.spi_host_csr_mem_rw_with_rand_reset.3568566971
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1336412 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13584) { a_addr: 'hd444beea a_data: 'h2506f466 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h20 a_opcode: 'h1 a_user: 'h24c6e d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1336412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13630) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.spi_host_csr_mem_rw_with_rand_reset.2021349695
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1146937 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13630) { a_addr: 'h3131f32a a_data: 'hec1cc425 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'hc1 a_opcode: 'h1 a_user: 'h26508 d_param: 'h0 d_source: 'hc1 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1146937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11268) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.spi_host_csr_mem_rw_with_rand_reset.1557912270
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1510773 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11268) { a_addr: 'he7eecf2a a_data: 'h9c238d94 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h72 a_opcode: 'h1 a_user: 'h2495b d_param: 'h0 d_source: 'h72 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1510773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11160) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.spi_host_csr_mem_rw_with_rand_reset.627464718
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1638574 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11160) { a_addr: 'h7ddb8f6a a_data: 'h8e109fbc a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hfa a_opcode: 'h1 a_user: 'h24795 d_param: 'h0 d_source: 'hfa d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1638574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11598) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.spi_host_csr_mem_rw_with_rand_reset.1306975384
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4483362 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11598) { a_addr: 'h6745d7a9 a_data: 'hc4123f2c a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h9f a_opcode: 'h1 a_user: 'h24e19 d_param: 'h0 d_source: 'h9f d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4483362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15068) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.spi_host_csr_mem_rw_with_rand_reset.528538742
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2642939 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15068) { a_addr: 'h7a888b6a a_data: 'haaa4c4d8 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h39 a_opcode: 'h0 a_user: 'h274d7 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2642939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11454) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.spi_host_csr_mem_rw_with_rand_reset.1025848020
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 7501291 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11454) { a_addr: 'h2005efaa a_data: 'hbdffef59 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h40 a_opcode: 'h1 a_user: 'h25892 d_param: 'h0 d_source: 'h40 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 7501291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:132) scoreboard [scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION has 1 failures:
34.spi_host_speed.93085398
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_speed/out/run.log
UVM_FATAL @ 51351324 ps: (spi_host_scoreboard.sv:132) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION
UVM_INFO @ 51351324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
37.spi_host_performance.781376996
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_performance/out/run.log
UVM_FATAL @ 10184524961 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3e5ee854) == 0x1
UVM_INFO @ 10184524961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:132) scoreboard [scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION has 1 failures:
43.spi_host_speed.37533381
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_speed/out/run.log
UVM_FATAL @ 137743165 ps: (spi_host_scoreboard.sv:132) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] FIRST SPI_ITEM DIDN'T CONTAIN FIRST BYE INDICATION
UVM_INFO @ 137743165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (spi_host_scoreboard.sv:143) scoreboard [scoreboard] has 1 failures:
48.spi_host_speed.3386018673
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_speed/out/run.log
UVM_FATAL @ 116193711 ps: (spi_host_scoreboard.sv:143) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
WRITE: actual data did not match exp data
len 6
byte actual expected
[ 0] a3 89