beb156d82beb156d82| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |
| V2 | performance | spi_host_performance | 47 | 50 | 94.00 |
| V2 | error_event_intr | spi_host_error_txrx | 0 | 0 | -- |
| spi_host_error_cmd | 0 | 0 | -- | ||
| spi_host_event | 0 | 0 | -- | ||
| V2 | clock_rate | spi_host_speed | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 0 | -- |
| V2 | cpol_cpha | spi_host_speed | 50 | 50 | 100.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | endian | endian | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 0 | 0 | -- |
| V2 | winbond | winbond | 0 | 0 | -- |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| TOTAL | 397 | 425 | 93.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 15 | 7 | 6 | 40.00 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 81.82 | 96.33 | 92.28 | 98.35 | 81.93 | 71.23 | 70.83 | 97.19 | 90.79 |
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
16.spi_host_performance.34960796
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_performance/out/run.log
UVM_FATAL @ 10195110522 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x46d3e794) == 0x1
UVM_INFO @ 10195110522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_performance.822359571
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_performance/out/run.log
UVM_FATAL @ 10086933873 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x113cec94) == 0x1
UVM_INFO @ 10086933873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10536) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_mem_partial_access.3716483645
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 4855362 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10536) { a_addr: 'h4a541c2a a_data: 'h8b0ca648 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hfb a_opcode: 'h0 a_user: 'h2697f d_param: 'h0 d_source: 'hfb d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4855362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13280) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_csr_mem_rw_with_rand_reset.2385185380
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3516067 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13280) { a_addr: 'hfcff7a6a a_data: 'h544ba1da a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'hc5 a_opcode: 'h1 a_user: 'h2647b d_param: 'h0 d_source: 'hc5 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3516067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13866) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_mem_partial_access.1382252730
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1303778 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13866) { a_addr: 'h75350f6a a_data: 'he6afc14a a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'hb3 a_opcode: 'h1 a_user: 'h255bf d_param: 'h0 d_source: 'hb3 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1303778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11139) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_csr_mem_rw_with_rand_reset.3260716301
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5086217 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11139) { a_addr: 'h64729aaa a_data: 'hb4e5c272 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h50 a_opcode: 'h1 a_user: 'h27a6b d_param: 'h0 d_source: 'h50 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5086217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12130) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_mem_partial_access.654910990
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2246086 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12130) { a_addr: 'hb375996b a_data: 'hc06aeef9 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h8f a_opcode: 'h0 a_user: 'h264db d_param: 'h0 d_source: 'h8f d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2246086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13111) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_csr_mem_rw_with_rand_reset.2827870185
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5135780 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13111) { a_addr: 'h44b2416a a_data: 'h99209943 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h4 a_opcode: 'h1 a_user: 'h2738b d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5135780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10579) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_mem_partial_access.747801693
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 732949 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10579) { a_addr: 'h11a1532b a_data: 'hafd325b8 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h90 a_opcode: 'h0 a_user: 'h24876 d_param: 'h0 d_source: 'h90 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 732949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13366) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_csr_mem_rw_with_rand_reset.3601227403
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2326497 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13366) { a_addr: 'h6a7a36aa a_data: 'h58addcb5 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hc a_opcode: 'h1 a_user: 'h261f6 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2326497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13757) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_mem_partial_access.1608365976
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1208347 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13757) { a_addr: 'h67605eaa a_data: 'h3581136d a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h24 a_opcode: 'h1 a_user: 'h26a37 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1208347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11343) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_csr_mem_rw_with_rand_reset.1275374789
Line 55, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 8209588 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11343) { a_addr: 'h43499029 a_data: 'h8785dae a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h39 a_opcode: 'h1 a_user: 'h27f36 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 8209588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14899) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.spi_host_csr_mem_rw_with_rand_reset.2196267243
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 6463905 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14899) { a_addr: 'h310555ab a_data: 'h6cdce167 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h5c a_opcode: 'h0 a_user: 'h2515b d_param: 'h0 d_source: 'h5c d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 6463905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11692) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.spi_host_csr_mem_rw_with_rand_reset.3711741040
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 7750893 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11692) { a_addr: 'h1c690e2a a_data: 'he28d87b3 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h7d a_opcode: 'h0 a_user: 'h25244 d_param: 'h0 d_source: 'h7d d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 7750893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13698) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.spi_host_csr_mem_rw_with_rand_reset.965124243
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2898003 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13698) { a_addr: 'h6f49a5e9 a_data: 'hf8d72979 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h64 a_opcode: 'h1 a_user: 'h270a8 d_param: 'h0 d_source: 'h64 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2898003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13632) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.spi_host_csr_mem_rw_with_rand_reset.367642561
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4661691 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13632) { a_addr: 'h4deee3aa a_data: 'h8394d519 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'h31 a_opcode: 'h1 a_user: 'h25513 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4661691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13447) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.spi_host_csr_mem_rw_with_rand_reset.909606149
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3663766 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13447) { a_addr: 'haa550aa9 a_data: 'h43afc247 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hac a_opcode: 'h1 a_user: 'h2427a d_param: 'h0 d_source: 'hac d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3663766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14841) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.spi_host_csr_mem_rw_with_rand_reset.58661291
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1831633 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14841) { a_addr: 'hba37baab a_data: 'hc290fa11 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hef a_opcode: 'h0 a_user: 'h25ab0 d_param: 'h0 d_source: 'hef d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1831633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15170) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.spi_host_csr_mem_rw_with_rand_reset.2198696058
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1745572 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15170) { a_addr: 'ha664c96a a_data: 'h7cc40f5e a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hb8 a_opcode: 'h0 a_user: 'h27f71 d_param: 'h0 d_source: 'hb8 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1745572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 1 failures:
12.spi_host_performance.2015834261
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_performance/out/run.log
UVM_FATAL @ 10118521258 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x34765254) == 0x0
UVM_INFO @ 10118521258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14794) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
12.spi_host_csr_mem_rw_with_rand_reset.4224057094
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 953773 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14794) { a_addr: 'h443a8feb a_data: 'ha2537815 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h2d a_opcode: 'h1 a_user: 'h26a84 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 953773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15253) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.spi_host_csr_mem_rw_with_rand_reset.970384766
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1005667 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15253) { a_addr: 'h9ee4c72a a_data: 'h878746b1 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hce a_opcode: 'h0 a_user: 'h27ea7 d_param: 'h0 d_source: 'hce d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1005667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14379) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.spi_host_csr_mem_rw_with_rand_reset.3620537492
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2721803 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14379) { a_addr: 'h2354b36a a_data: 'h7e8e0fc2 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h3e a_opcode: 'h1 a_user: 'h255bc d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2721803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14539) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.spi_host_csr_mem_rw_with_rand_reset.962357902
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1779119 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14539) { a_addr: 'hcdbbbfea a_data: 'ha604b4ff a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h44 a_opcode: 'h1 a_user: 'h25c9b d_param: 'h0 d_source: 'h44 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1779119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.spi_host_csr_mem_rw_with_rand_reset.3480891943
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1022738 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14778) { a_addr: 'h4545bbea a_data: 'h830b19e7 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'hcb a_opcode: 'h1 a_user: 'h27930 d_param: 'h0 d_source: 'hcb d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1022738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14950) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.spi_host_csr_mem_rw_with_rand_reset.739054861
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4949814 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14950) { a_addr: 'h435ca62a a_data: 'h13d4749a a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h5c a_opcode: 'h0 a_user: 'h27209 d_param: 'h0 d_source: 'h5c d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4949814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15070) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.spi_host_csr_mem_rw_with_rand_reset.3310438
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1098374 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15070) { a_addr: 'hda928a2b a_data: 'h9e3b146e a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h51 a_opcode: 'h0 a_user: 'h24d3f d_param: 'h0 d_source: 'h51 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1098374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15174) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.spi_host_csr_mem_rw_with_rand_reset.1630816435
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2144501 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15174) { a_addr: 'hdcb07d6a a_data: 'hc71ad83d a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h3d a_opcode: 'h0 a_user: 'h26769 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2144501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---