a13b9b8eda13b9b8ed| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |
| V2 | performance | spi_host_performance | 46 | 50 | 92.00 |
| V2 | error_event_intr | spi_host_error_txrx | 0 | 0 | -- |
| spi_host_error_cmd | 0 | 0 | -- | ||
| spi_host_event | 0 | 0 | -- | ||
| V2 | clock_rate | spi_host_speed | 49 | 50 | 98.00 |
| V2 | speed | spi_host_speed | 49 | 50 | 98.00 |
| V2 | chip_select_timing | spi_host_speed | 49 | 50 | 98.00 |
| V2 | sw_reset | spi_host_sw_reset | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 0 | -- |
| V2 | cpol_cpha | spi_host_speed | 49 | 50 | 98.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | endian | endian | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 0 | 0 | -- |
| V2 | winbond | winbond | 0 | 0 | -- |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| TOTAL | 395 | 425 | 92.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 15 | 7 | 5 | 33.33 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 81.86 | 96.33 | 92.28 | 98.35 | 81.76 | 71.35 | 70.83 | 97.19 | 90.79 |
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 2 failures:
Test spi_host_performance has 1 failures.
0.spi_host_performance.2515246055
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_performance/out/run.log
UVM_FATAL @ 10541435966 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xc2fbac94) == 0x0
UVM_INFO @ 10541435966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
28.spi_host_speed.1824932754
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/out/run.log
UVM_FATAL @ 10074839875 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x15adfed4) == 0x0
UVM_INFO @ 10074839875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11938) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_mem_partial_access.2443475819
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 4991767 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11938) { a_addr: 'hfddc3f2a a_data: 'h95d2041d a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hf7 a_opcode: 'h1 a_user: 'h2722d d_param: 'h0 d_source: 'hf7 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4991767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13486) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_csr_mem_rw_with_rand_reset.1724645869
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1556931 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13486) { a_addr: 'h1932a3ab a_data: 'h69d6964c a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'he3 a_opcode: 'h0 a_user: 'h268a9 d_param: 'h0 d_source: 'he3 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1556931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11960) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_mem_partial_access.1010219020
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2515041 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11960) { a_addr: 'h84ea0eaa a_data: 'hdf654be a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h89 a_opcode: 'h1 a_user: 'h24551 d_param: 'h0 d_source: 'h89 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2515041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15151) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_csr_mem_rw_with_rand_reset.3744027277
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1109068 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15151) { a_addr: 'he9f4c56b a_data: 'h5e7ea8b2 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h62 a_opcode: 'h0 a_user: 'h25bb8 d_param: 'h0 d_source: 'h62 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1109068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
2.spi_host_performance.777098322
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_performance/out/run.log
UVM_FATAL @ 10096927157 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc76eddd4) == 0x1
UVM_INFO @ 10096927157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13519) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_mem_partial_access.2678493202
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2494355 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13519) { a_addr: 'h6c5d88ea a_data: 'hb74703a3 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h87 a_opcode: 'h1 a_user: 'h276ac d_param: 'h0 d_source: 'h87 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2494355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13498) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_csr_mem_rw_with_rand_reset.1321637189
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 896483 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13498) { a_addr: 'h46bb8ba9 a_data: 'h6c572462 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hf5 a_opcode: 'h0 a_user: 'h27143 d_param: 'h0 d_source: 'hf5 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 896483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10860) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_mem_partial_access.2624623620
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1159570 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10860) { a_addr: 'h3cdeddea a_data: 'heb186cb5 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'he a_opcode: 'h1 a_user: 'h2415c d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1159570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11215) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_csr_mem_rw_with_rand_reset.553953077
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 6346000 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11215) { a_addr: 'hc7fa5dea a_data: 'h3bd9c863 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h3f a_opcode: 'h1 a_user: 'h271ba d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 6346000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10818) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_mem_partial_access.3897304007
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1242177 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10818) { a_addr: 'h1b2ace6a a_data: 'hc804948 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h91 a_opcode: 'h0 a_user: 'h270e7 d_param: 'h0 d_source: 'h91 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1242177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11805) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_csr_mem_rw_with_rand_reset.1192929059
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5159930 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11805) { a_addr: 'he1ffa8ab a_data: 'h87a315fa a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hdf a_opcode: 'h0 a_user: 'h2729b d_param: 'h0 d_source: 'hdf d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5159930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.spi_host_csr_mem_rw_with_rand_reset.164411172
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1096268 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11124) { a_addr: 'h4df62e2a a_data: 'h6c7f7c8c a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'h7e a_opcode: 'h1 a_user: 'h25ead d_param: 'h0 d_source: 'h7e d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1096268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13365) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.spi_host_csr_mem_rw_with_rand_reset.890688213
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2534902 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13365) { a_addr: 'hf6b2bf6a a_data: 'h1cad00b6 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'hc5 a_opcode: 'h1 a_user: 'h25b74 d_param: 'h0 d_source: 'hc5 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2534902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11234) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.spi_host_csr_mem_rw_with_rand_reset.973489935
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1821234 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11234) { a_addr: 'had3a792a a_data: 'heffb36d9 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'hdb a_opcode: 'h1 a_user: 'h24bc2 d_param: 'h0 d_source: 'hdb d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1821234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11272) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.spi_host_csr_mem_rw_with_rand_reset.3772503399
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2107314 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11272) { a_addr: 'h2ccda02a a_data: 'hb8c6b0ab a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h1e a_opcode: 'h0 a_user: 'h24ad2 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2107314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13333) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.spi_host_csr_mem_rw_with_rand_reset.1311100195
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2425288 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13333) { a_addr: 'hca70276b a_data: 'h43c7bbe4 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h90 a_opcode: 'h1 a_user: 'h25276 d_param: 'h0 d_source: 'h90 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2425288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
10.spi_host_performance.1018169249
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_performance/out/run.log
UVM_FATAL @ 10092201386 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x203ed2d4) == 0x1
UVM_INFO @ 10092201386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13174) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.spi_host_csr_mem_rw_with_rand_reset.3604612367
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2209839 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13174) { a_addr: 'h576f096b a_data: 'he7c74a4f a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hd2 a_opcode: 'h1 a_user: 'h24fc4 d_param: 'h0 d_source: 'hd2 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2209839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11205) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.spi_host_csr_mem_rw_with_rand_reset.2732603398
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3756857 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11205) { a_addr: 'h2927cce9 a_data: 'h5319a46c a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h81 a_opcode: 'h1 a_user: 'h247a0 d_param: 'h0 d_source: 'h81 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3756857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11300) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
12.spi_host_csr_mem_rw_with_rand_reset.4252447216
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3648249 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11300) { a_addr: 'h4bbfc56a a_data: 'he9f2086f a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h91 a_opcode: 'h0 a_user: 'h244a2 d_param: 'h0 d_source: 'h91 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3648249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13553) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.spi_host_csr_mem_rw_with_rand_reset.3695536425
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2659397 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13553) { a_addr: 'h709f09e9 a_data: 'h8fb55e1b a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hfc a_opcode: 'h0 a_user: 'h25fe3 d_param: 'h0 d_source: 'hfc d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2659397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14492) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.spi_host_csr_mem_rw_with_rand_reset.1340713960
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5609971 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14492) { a_addr: 'hb1660caa a_data: 'habf84f44 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h5c a_opcode: 'h0 a_user: 'h275ba d_param: 'h0 d_source: 'h5c d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5609971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13609) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.spi_host_csr_mem_rw_with_rand_reset.2238561462
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2260475 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13609) { a_addr: 'hcfc1c52a a_data: 'h3be88add a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h19 a_opcode: 'h0 a_user: 'h27cfc d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2260475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13309) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.spi_host_csr_mem_rw_with_rand_reset.3536257025
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4028374 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13309) { a_addr: 'h196a1dab a_data: 'h8928d3f7 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h3f a_opcode: 'h0 a_user: 'h24898 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4028374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13458) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.spi_host_csr_mem_rw_with_rand_reset.2658561599
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1578975 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13458) { a_addr: 'h9c80526b a_data: 'h7557a148 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hd3 a_opcode: 'h0 a_user: 'h25f39 d_param: 'h0 d_source: 'hd3 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1578975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11240) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.spi_host_csr_mem_rw_with_rand_reset.2264090527
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5038560 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11240) { a_addr: 'h7974fa6a a_data: 'h538b713a a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h70 a_opcode: 'h1 a_user: 'h26ae8 d_param: 'h0 d_source: 'h70 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5038560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 1 failures:
19.spi_host_performance.1668374637
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_performance/out/run.log
UVM_FATAL @ 10136571567 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x14643454) == 0x0
UVM_INFO @ 10136571567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15089) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.spi_host_csr_mem_rw_with_rand_reset.4069622703
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3941601 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15089) { a_addr: 'he6b7d96a a_data: 'h9e17bc71 a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'h36 a_opcode: 'h1 a_user: 'h24a0b d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3941601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---