8d5fa645a8d5fa645a| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 85 | 105 | 80.95 | |
| V2 | performance | spi_host_performance | 45 | 50 | 90.00 |
| V2 | error_event_intr | spi_host_error_txrx | 0 | 0 | -- |
| spi_host_error_cmd | 0 | 0 | -- | ||
| spi_host_event | 0 | 0 | -- | ||
| V2 | clock_rate | spi_host_speed | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 48 | 50 | 96.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 0 | 0 | -- |
| V2 | cpol_cpha | spi_host_speed | 50 | 50 | 100.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | endian | endian | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 0 | 0 | -- |
| V2 | winbond | winbond | 0 | 0 | -- |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 290 | 97.59 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 0 | 5 | 0.00 | ||
| TOTAL | 393 | 425 | 92.47 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 1 | 50.00 |
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 15 | 7 | 5 | 33.33 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 81.81 | 96.33 | 92.28 | 98.35 | 81.40 | 71.35 | 70.83 | 97.19 | 90.79 |
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
Test spi_host_performance has 2 failures.
2.spi_host_performance.3229115595
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_performance/out/run.log
UVM_FATAL @ 10092120877 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd6aca614) == 0x1
UVM_INFO @ 10092120877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_performance.2978564725
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_performance/out/run.log
UVM_FATAL @ 10049526264 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcfb60c94) == 0x1
UVM_INFO @ 10049526264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
19.spi_host_sw_reset.3289921452
Line 173, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/out/run.log
UVM_FATAL @ 10759098095 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc4157254) == 0x1
UVM_INFO @ 10759098095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 3 failures:
4.spi_host_performance.2492519841
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_performance/out/run.log
UVM_FATAL @ 10464104242 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x8b38c514) == 0x0
UVM_INFO @ 10464104242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_performance.7032762
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_performance/out/run.log
UVM_FATAL @ 10305121074 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xfbd6414) == 0x0
UVM_INFO @ 10305121074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_mem_partial_access.63470431
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 860409 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10663) { a_addr: 'h75932aea a_data: 'h3432857e a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h7e a_opcode: 'h1 a_user: 'h27306 d_param: 'h0 d_source: 'h7e d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 860409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13361) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.spi_host_csr_mem_rw_with_rand_reset.474361090
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2300625 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13361) { a_addr: 'hbef1dae9 a_data: 'h7ee02178 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h3e a_opcode: 'h0 a_user: 'h267a4 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2300625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12099) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_mem_partial_access.3980079193
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1515511 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12099) { a_addr: 'hb611dcaa a_data: 'hec49297d a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hc5 a_opcode: 'h0 a_user: 'h240dc d_param: 'h0 d_source: 'hc5 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1515511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11841) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.spi_host_csr_mem_rw_with_rand_reset.3584282150
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1691789 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11841) { a_addr: 'hc79610ab a_data: 'hf9068a7e a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hcf a_opcode: 'h0 a_user: 'h2507b d_param: 'h0 d_source: 'hcf d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1691789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12186) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_mem_partial_access.1833116413
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 2806999 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@12186) { a_addr: 'h6037dab a_data: 'h2c8896cc a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'he1 a_opcode: 'h0 a_user: 'h24442 d_param: 'h0 d_source: 'he1 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2806999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11378) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.spi_host_csr_mem_rw_with_rand_reset.1114598069
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 7267655 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11378) { a_addr: 'hd1bed36a a_data: 'h8c7aa063 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h24 a_opcode: 'h0 a_user: 'h26968 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 7267655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13884) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_mem_partial_access.2519883466
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 1530204 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13884) { a_addr: 'h64a3452a a_data: 'h81c0dbb6 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h94 a_opcode: 'h0 a_user: 'h2712e d_param: 'h0 d_source: 'h94 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1530204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13702) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.spi_host_csr_mem_rw_with_rand_reset.4071079812
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 3211152 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13702) { a_addr: 'h399e5ea a_data: 'habbc3915 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hed a_opcode: 'h1 a_user: 'h26bbf d_param: 'h0 d_source: 'hed d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 3211152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10562) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_mem_partial_access.1243197778
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_mem_partial_access/out/run.log
UVM_ERROR @ 4690248 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@10562) { a_addr: 'he59142a a_data: 'h2af4b8e8 a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'hd3 a_opcode: 'h0 a_user: 'h27970 d_param: 'h0 d_source: 'hd3 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4690248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14871) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.spi_host_csr_mem_rw_with_rand_reset.1885649792
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1398684 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14871) { a_addr: 'hfba92c2b a_data: 'ha00d8de2 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h260ef d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1398684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11174) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.spi_host_csr_mem_rw_with_rand_reset.1730861128
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2208047 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11174) { a_addr: 'hfebccc6b a_data: 'heb44ac45 a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'h1f a_opcode: 'h1 a_user: 'h269ef d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2208047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11207) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.spi_host_csr_mem_rw_with_rand_reset.1994492245
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5125391 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11207) { a_addr: 'h1361402a a_data: 'h6626c7d a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'h6f a_opcode: 'h0 a_user: 'h2661b d_param: 'h0 d_source: 'h6f d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5125391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11192) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.spi_host_csr_mem_rw_with_rand_reset.3443728829
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5685864 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11192) { a_addr: 'ha7ce13ea a_data: 'h913fd5f0 a_mask: 'hc a_size: 'h1 a_param: 'h0 a_source: 'hc7 a_opcode: 'h0 a_user: 'h24599 d_param: 'h0 d_source: 'hc7 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5685864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11912) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.spi_host_csr_mem_rw_with_rand_reset.892428309
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2940181 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11912) { a_addr: 'hf7bc6e69 a_data: 'h91990c6b a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h7c a_opcode: 'h0 a_user: 'h25dd2 d_param: 'h0 d_source: 'h7c d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2940181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11002) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.spi_host_csr_mem_rw_with_rand_reset.2794656010
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1779656 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11002) { a_addr: 'hfcd932aa a_data: 'hf01bf34f a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h48 a_opcode: 'h1 a_user: 'h25f3a d_param: 'h0 d_source: 'h48 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1779656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14927) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.spi_host_csr_mem_rw_with_rand_reset.2268282749
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2464329 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@14927) { a_addr: 'hccedac2a a_data: 'h997cdb0f a_mask: 'h4 a_size: 'h0 a_param: 'h0 a_source: 'h86 a_opcode: 'h0 a_user: 'h24b11 d_param: 'h0 d_source: 'h86 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2464329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11462) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.spi_host_csr_mem_rw_with_rand_reset.4094964594
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2519746 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11462) { a_addr: 'heb6eb16a a_data: 'hfb8bf2aa a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'hb7 a_opcode: 'h1 a_user: 'h259dd d_param: 'h0 d_source: 'hb7 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2519746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11267) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
12.spi_host_csr_mem_rw_with_rand_reset.3648585848
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1754919 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11267) { a_addr: 'h5399b6aa a_data: 'h21961cc5 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'hf a_opcode: 'h1 a_user: 'h2577e d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1754919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13302) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.spi_host_csr_mem_rw_with_rand_reset.3092318109
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 1375845 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13302) { a_addr: 'h67d94329 a_data: 'hcb04c26 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h4e a_opcode: 'h0 a_user: 'h2541d d_param: 'h0 d_source: 'h4e d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 1375845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15979) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.spi_host_csr_mem_rw_with_rand_reset.4030647190
Line 55, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2798144 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15979) { a_addr: 'h60f141aa a_data: 'h51bea8cd a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h32 a_opcode: 'h1 a_user: 'h27a39 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2798144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11164) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.spi_host_csr_mem_rw_with_rand_reset.1105245362
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5974870 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11164) { a_addr: 'hdb06a6e9 a_data: 'h1004f4a8 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'hd0 a_opcode: 'h0 a_user: 'h240ee d_param: 'h0 d_source: 'hd0 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5974870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.spi_host_csr_mem_rw_with_rand_reset.874101707
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 5028576 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@11663) { a_addr: 'hc214786a a_data: 'h7b514196 a_mask: 'h4 a_size: 'h1 a_param: 'h0 a_source: 'h52 a_opcode: 'h1 a_user: 'h25b66 d_param: 'h0 d_source: 'h52 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 5028576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13423) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.spi_host_csr_mem_rw_with_rand_reset.414769422
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4035036 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@13423) { a_addr: 'hdaa02a6b a_data: 'hdb9e173c a_mask: 'h8 a_size: 'h0 a_param: 'h0 a_source: 'hdc a_opcode: 'h0 a_user: 'h264ba d_param: 'h0 d_source: 'hdc d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 4035036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15110) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.spi_host_csr_mem_rw_with_rand_reset.193667217
Line 49, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 6691197 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@15110) { a_addr: 'heb438969 a_data: 'hb21d10d2 a_mask: 'h2 a_size: 'h0 a_param: 'h0 a_source: 'h45 a_opcode: 'h1 a_user: 'h26da8 d_param: 'h0 d_source: 'h45 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h16aa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 6691197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:422) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@16594) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.spi_host_csr_mem_rw_with_rand_reset.2005274973
Line 55, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 2215137 ps: (cip_base_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface spi_host_reg_block, TL item: req: (cip_tl_seq_item@16594) { a_addr: 'hd6f3f22a a_data: 'h74f18da2 a_mask: 'h8 a_size: 'h1 a_param: 'h0 a_source: 'h1f a_opcode: 'h1 a_user: 'h27561 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h132a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0
UVM_INFO @ 2215137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---