6a92ed2656a92ed265| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | performance | spi_host_performance | 11 | 50 | 22.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 0 | 50 | 0.00 |
| spi_host_error_cmd | 2 | 50 | 4.00 | ||
| spi_host_event | 0 | 50 | 0.00 | ||
| V2 | clock_rate | spi_host_speed | 49 | 50 | 98.00 |
| V2 | speed | spi_host_speed | 49 | 50 | 98.00 |
| V2 | chip_select_timing | spi_host_speed | 49 | 50 | 98.00 |
| V2 | sw_reset | spi_host_sw_reset | 48 | 50 | 96.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 49 | 50 | 98.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 2 | 50 | 4.00 |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 302 | 540 | 55.93 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | winbond | winbond | 0 | 0 | -- |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 5 | 5 | 100.00 | ||
| TOTAL | 437 | 675 | 64.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 2 | 100.00 |
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 12 | 5 | 38.46 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 80.21 | 95.15 | 89.47 | 97.02 | 81.64 | 69.02 | 66.67 | 96.00 | 91.21 |
UVM_WARNING [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory. has 65 failures:
0.spi_host_overflow_underflow.3845556169
Line 45, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_overflow_underflow/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.spi_host_overflow_underflow.968114198
Line 45, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_overflow_underflow/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.spi_host_stress_all.1951809037
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/out/run.log
UVM_WARNING @ 1325551905 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 1325551905 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
10.spi_host_stress_all.452449389
Line 47, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/out/run.log
UVM_WARNING @ 1966907 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 1966907 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.txwm has 62 failures:
0.spi_host_event.2470032217
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_event/out/run.log
UVM_ERROR @ 31747584 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 31747584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_event.1041927508
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_event/out/run.log
UVM_ERROR @ 5090743 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 5090743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
4.spi_host_stress_all.1058753839
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/out/run.log
UVM_ERROR @ 2292159 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 2292159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_stress_all.4007319247
Line 245, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/out/run.log
UVM_ERROR @ 4216616629 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 4216616629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 27 failures:
Test spi_host_speed has 1 failures.
1.spi_host_speed.1645887890
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/out/run.log
UVM_FATAL @ 10027506012 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xcaa0a354) == 0x0
UVM_INFO @ 10027506012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_performance has 20 failures.
3.spi_host_performance.2416346734
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_performance/out/run.log
UVM_FATAL @ 10197138268 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xbbc51dd4) == 0x0
UVM_INFO @ 10197138268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_performance.405606321
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_performance/out/run.log
UVM_FATAL @ 10061554233 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xcf0a9494) == 0x0
UVM_INFO @ 10061554233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test spi_host_sw_reset has 1 failures.
16.spi_host_sw_reset.459711609
Line 83, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/out/run.log
UVM_FATAL @ 10578389985 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x31158d94) == 0x0
UVM_INFO @ 10578389985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 5 failures.
31.spi_host_stress_all.2574834498
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_stress_all/out/run.log
UVM_FATAL @ 10183968076 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x4e233654) == 0x0
UVM_INFO @ 10183968076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_stress_all.2795556551
Line 245, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_stress_all/out/run.log
UVM_FATAL @ 16160262975 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xcb6bc254) == 0x0
UVM_INFO @ 16160262975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state has 25 failures:
1.spi_host_error_cmd.3824217233
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_error_cmd/out/run.log
UVM_ERROR @ 6544812 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 6544812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_error_cmd.1039236680
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_error_cmd/out/run.log
UVM_ERROR @ 2025153 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 2025153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
2.spi_host_stress_all.3719502874
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/out/run.log
UVM_ERROR @ 4907686 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 4907686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_stress_all.1420329611
Line 119, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_stress_all/out/run.log
UVM_ERROR @ 463872729 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 463872729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
3.spi_host_error_cmd.1579176029
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_error_cmd/out/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_error_cmd.603436930
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_error_cmd/out/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 15 failures:
1.spi_host_performance.1606896019
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_performance/out/run.log
UVM_FATAL @ 10215186413 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xccef1094) == 0x1
UVM_INFO @ 10215186413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_performance.1444452086
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_performance/out/run.log
UVM_FATAL @ 10035882824 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd348df54) == 0x1
UVM_INFO @ 10035882824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
3.spi_host_stress_all.3035338793
Line 83, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/out/run.log
UVM_FATAL @ 10760741093 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x825d9254) == 0x1
UVM_INFO @ 10760741093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_stress_all.882998683
Line 173, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/out/run.log
UVM_FATAL @ 17449972595 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x53330554) == 0x1
UVM_INFO @ 17449972595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:378) [spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 11 failures:
6.spi_host_error_cmd.1730886234
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_error_cmd/out/run.log
UVM_ERROR @ 3719555 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3719555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_error_cmd.6122166
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_error_cmd/out/run.log
UVM_ERROR @ 11555308 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 11555308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 5 failures:
Test spi_host_sw_reset has 1 failures.
20.spi_host_sw_reset.2426647237
Line 101, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/out/run.log
UVM_FATAL @ 10184893740 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3366d7d4) == 0x1
UVM_INFO @ 10184893740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
30.spi_host_stress_all.678781919
Line 83, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_stress_all/out/run.log
UVM_FATAL @ 11233763779 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x95177254) == 0x1
UVM_INFO @ 11233763779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_performance has 3 failures.
32.spi_host_performance.2785552846
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_performance/out/run.log
UVM_FATAL @ 10047812907 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb4e7eb54) == 0x1
UVM_INFO @ 10047812907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_performance.3055725233
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_performance/out/run.log
UVM_FATAL @ 10057112720 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb491ead4) == 0x1
UVM_INFO @ 10057112720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:378) [spi_host_event_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 3 failures:
1.spi_host_stress_all.207583528
Line 83, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/out/run.log
UVM_ERROR @ 643580901 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_event_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_INFO @ 643580901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_stress_all.3486165467
Line 83, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/out/run.log
UVM_ERROR @ 1038781874 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_event_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1038781874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.error_status.cmdbusy has 3 failures:
13.spi_host_error_cmd.3561679968
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_error_cmd/out/run.log
UVM_ERROR @ 24415840 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.error_status.cmdbusy
UVM_INFO @ 24415840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_error_cmd.139427882
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_error_cmd/out/run.log
UVM_ERROR @ 8550294 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.error_status.cmdbusy
UVM_INFO @ 8550294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
2.spi_host_performance.4173674691
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_performance/out/run.log
UVM_FATAL @ 10044261841 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8c3c6f54) == 0x0
UVM_INFO @ 10044261841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.spi_host_performance.1665422600
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_performance/out/run.log
UVM_FATAL @ 10049214426 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8cb4fb94) == 0x0
UVM_INFO @ 10049214426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 2 failures:
34.spi_host_performance.4030351672
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_performance/out/run.log
UVM_FATAL @ 10079951677 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xa2b535d4) == 0x0
UVM_INFO @ 10079951677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_performance.1067442891
Line 65, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_performance/out/run.log
UVM_FATAL @ 10232757315 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x18e264d4) == 0x0
UVM_INFO @ 10232757315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
28.spi_host_stress_all.3984830568
Line 227, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/out/run.log
UVM_FATAL @ 19973951486 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x94bcf054) == 0x0
UVM_INFO @ 19973951486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---