SPI_HOST Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.033m	25.579ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	17.006us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	51.181us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	34.928us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	30.994us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	26.845us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	51.181us	20	20	100.00
		spi_host_csr_aliasing	3.000s	30.994us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	107.694us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	24.531us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	4.000s	30.024us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.683m	13.989ms	48	50	96.00
		spi_host_error_cmd	3.000s	17.224us	50	50	100.00
		spi_host_event	22.567m	331.590ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.850m	29.193ms	50	50	100.00
V2	speed	spi_host_speed	5.850m	29.193ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.850m	29.193ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	5.350m	13.756ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	446.889us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.850m	29.193ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.850m	29.193ms	50	50	100.00
V2	duplex	spi_host_smoke	10.033m	25.579ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	10.033m	25.579ms	49	50	98.00
V2	stress_all	spi_host_stress_all	2.100m	16.504ms	48	50	96.00
V2	spien	spi_host_spien	6.800m	38.203ms	49	50	98.00
V2	stall	spi_host_status_stall	12.533m	17.833ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.317m	1.788ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	23.194us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	200.813us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	500.972us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	500.972us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	17.006us	5	5	100.00
		spi_host_csr_rw	4.000s	51.181us	20	20	100.00
		spi_host_csr_aliasing	3.000s	30.994us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	373.246us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	17.006us	5	5	100.00
		spi_host_csr_rw	4.000s	51.181us	20	20	100.00
		spi_host_csr_aliasing	3.000s	30.994us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	373.246us	20	20	100.00
V2		TOTAL			678	690	98.26
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	272.293us	20	20	100.00
		spi_host_sec_cm	2.000s	61.766us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	272.293us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			817	830	98.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.19	95.98	99.74	96.16	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 5 failures:

Test spi_host_sw_reset has 4 failures.

2.spi_host_sw_reset.2750652772
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 12065839576 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbc923614) == 0x0
  UVM_INFO @ 12065839576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.spi_host_sw_reset.1147449820
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 15689009670 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x742029d4) == 0x0
  UVM_INFO @ 15689009670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test spi_host_stress_all has 1 failures.

3.spi_host_stress_all.713390966
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 10005179957 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x93ea3d14) == 0x0
  UVM_INFO @ 10005179957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:

Test spi_host_overflow_underflow has 2 failures.

21.spi_host_overflow_underflow.1173199091
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 44922649340 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7f283254) == 0x0
  UVM_INFO @ 44922649340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.spi_host_overflow_underflow.809500885
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 55121746462 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe5d7e654) == 0x0
  UVM_INFO @ 55121746462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_stress_all has 1 failures.

23.spi_host_stress_all.4056068651
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 28586560620 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4dec3a54) == 0x0
  UVM_INFO @ 28586560620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_sw_reset has 1 failures.

38.spi_host_sw_reset.4184223892
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 16972349843 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x188e9554) == 0x0
  UVM_INFO @ 16972349843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 1 failures.

48.spi_host_smoke.3458804718
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_smoke/latest/run.log

  UVM_FATAL @ 119614991179 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa7353594) == 0x0
  UVM_INFO @ 119614991179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test spi_host_status_stall has 2 failures.

4.spi_host_status_stall.2949803524
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.spi_host_status_stall.2903643385
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 9.spi_host_spien.3303407536
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 13273048460 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xff0afb94) == 0x1
  UVM_INFO @ 13273048460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```