SPI_HOST Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.550m	13.454ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	57.427us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	14.855us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	315.888us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	72.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	37.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	14.855us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.792us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	15.439us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	66.196us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	94.452us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.150m	5.900ms	50	50	100.00
		spi_host_error_cmd	3.000s	52.248us	50	50	100.00
		spi_host_event	26.083m	167.227ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.867m	15.907ms	50	50	100.00
V2	speed	spi_host_speed	5.867m	15.907ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.867m	15.907ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	7.967m	10.953ms	46	50	92.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	892.167us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.867m	15.907ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.867m	15.907ms	50	50	100.00
V2	duplex	spi_host_smoke	9.550m	13.454ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	9.550m	13.454ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.300m	9.268ms	48	50	96.00
V2	spien	spi_host_spien	6.550m	9.193ms	50	50	100.00
V2	stall	spi_host_status_stall	10.600m	34.389ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.150m	18.557ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	49.547us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	22.098us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	121.305us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	121.305us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	57.427us	5	5	100.00
		spi_host_csr_rw	3.000s	14.855us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.792us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	35.418us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	57.427us	5	5	100.00
		spi_host_csr_rw	3.000s	14.855us	20	20	100.00
		spi_host_csr_aliasing	3.000s	72.792us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	35.418us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	83.373us	20	20	100.00
		spi_host_sec_cm	3.000s	70.525us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	83.373us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.07	98.19	95.98	99.74	96.16	95.70	100.00	98.60	91.29

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:

Test spi_host_smoke has 2 failures.

1.spi_host_smoke.776938646
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log

  UVM_FATAL @ 67095779535 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x96ef8b54) == 0x0
  UVM_INFO @ 67095779535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.spi_host_smoke.980142720
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log

  UVM_FATAL @ 82705136992 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x445d7ad4) == 0x0
  UVM_INFO @ 82705136992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_stress_all has 2 failures.

17.spi_host_stress_all.1264768653
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 14038247855 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd8f92414) == 0x0
  UVM_INFO @ 14038247855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.spi_host_stress_all.1478504768
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 21433760477 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe10d394) == 0x0
  UVM_INFO @ 21433760477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:

Test spi_host_sw_reset has 3 failures.

16.spi_host_sw_reset.2927443094
Line 305, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10952939872 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbc7fc454) == 0x0
  UVM_INFO @ 10952939872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.spi_host_sw_reset.759930481
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10001327221 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe73c4d54) == 0x0
  UVM_INFO @ 10001327221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 25.spi_host_status_stall.2766711570
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 29.spi_host_status_stall.82848253
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 32.spi_host_sw_reset.2962143695
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10003794148 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7530c794) == 0x0
  UVM_INFO @ 10003794148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```