26b0ee226| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.183m | 12.628ms | 47 | 50 | 94.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 56.477us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 25.121us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 159.869us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 29.200us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 91.545us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 25.121us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 29.200us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 16.593us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 20.444us | 5 | 5 | 100.00 |
| V1 | TOTAL | 112 | 115 | 97.39 | |||
| V2 | performance | spi_host_performance | 5.000s | 95.686us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.950m | 4.257ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 3.000s | 196.773us | 50 | 50 | 100.00 | ||
| spi_host_event | 22.900m | 168.007ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.950m | 16.123ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 5.950m | 16.123ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 5.950m | 16.123ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.600m | 10.211ms | 44 | 50 | 88.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 616.932us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.950m | 16.123ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 5.950m | 16.123ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 10.183m | 12.628ms | 47 | 50 | 94.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.183m | 12.628ms | 47 | 50 | 94.00 |
| V2 | stress_all | spi_host_stress_all | 4.483m | 6.009ms | 48 | 50 | 96.00 |
| V2 | spien | spi_host_spien | 6.467m | 8.516ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 11.733m | 62.802ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 1.283m | 1.604ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 5.000s | 18.024us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 48.188us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 6.000s | 89.896us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 6.000s | 89.896us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 56.477us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 25.121us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 29.200us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 36.051us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 56.477us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 25.121us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 29.200us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 36.051us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 678 | 690 | 98.26 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 86.719us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 3.751ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 86.719us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 815 | 830 | 98.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 11 | 73.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.07 | 98.19 | 95.98 | 99.74 | 96.16 | 95.70 | 100.00 | 98.60 | 91.29 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
Test spi_host_overflow_underflow has 1 failures.
0.spi_host_overflow_underflow.4165802746
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 41689184608 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x71f24414) == 0x0
UVM_INFO @ 41689184608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
13.spi_host_stress_all.2457644586
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15086725504 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x515228d4) == 0x0
UVM_INFO @ 15086725504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_stress_all.467609297
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log
UVM_FATAL @ 13842010137 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe66e2994) == 0x0
UVM_INFO @ 13842010137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 2 failures.
18.spi_host_sw_reset.1095800621
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10088350094 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbd8e7c94) == 0x0
UVM_INFO @ 10088350094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_sw_reset.2077571675
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 19926290847 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe74b3294) == 0x0
UVM_INFO @ 19926290847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
48.spi_host_smoke.2971513412
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_smoke/latest/run.log
UVM_FATAL @ 74043723062 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x807cf314) == 0x0
UVM_INFO @ 74043723062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
28.spi_host_status_stall.3675855291
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_status_stall.2750932942
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
12.spi_host_smoke.3315769663
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 60278767705 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x282d9e94) == 0x0
UVM_INFO @ 60278767705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_smoke.1896790342
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_smoke/latest/run.log
UVM_FATAL @ 142257588242 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8ac9d554) == 0x0
UVM_INFO @ 142257588242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
19.spi_host_sw_reset.1123763118
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 11774966947 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa52291d4) == 0x0
UVM_INFO @ 11774966947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_host_sw_reset.2288549907
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007885203 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x951c6b54) == 0x0
UVM_INFO @ 10007885203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:
29.spi_host_sw_reset.1109616519
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10012846346 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x72ecb94) == 0x0
UVM_INFO @ 10012846346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_sw_reset.1757839598
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10210977326 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x80696c94) == 0x0
UVM_INFO @ 10210977326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---