SPI_HOST Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.500m	54.440ms	48	50	96.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	16.026us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	50.977us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	161.278us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	35.176us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	30.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	50.977us	20	20	100.00
		spi_host_csr_aliasing	3.000s	35.176us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	13.984us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	18.511us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	performance	spi_host_performance	4.000s	69.881us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.933m	10.026ms	49	50	98.00
		spi_host_error_cmd	3.000s	46.045us	50	50	100.00
		spi_host_event	21.817m	29.575ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.250m	37.419ms	50	50	100.00
V2	speed	spi_host_speed	5.250m	37.419ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.250m	37.419ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.950m	12.177ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	872.329us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.250m	37.419ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.250m	37.419ms	50	50	100.00
V2	duplex	spi_host_smoke	10.500m	54.440ms	48	50	96.00
V2	tx_rx_only	spi_host_smoke	10.500m	54.440ms	48	50	96.00
V2	stress_all	spi_host_stress_all	3.183m	4.278ms	49	50	98.00
V2	spien	spi_host_spien	6.617m	98.809ms	49	50	98.00
V2	stall	spi_host_status_stall	12.817m	17.511ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.267m	3.103ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	28.796us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	17.262us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	76.824us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	76.824us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	16.026us	5	5	100.00
		spi_host_csr_rw	3.000s	50.977us	20	20	100.00
		spi_host_csr_aliasing	3.000s	35.176us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	22.833us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	16.026us	5	5	100.00
		spi_host_csr_rw	3.000s	50.977us	20	20	100.00
		spi_host_csr_aliasing	3.000s	35.176us	5	5	100.00
		spi_host_same_csr_outstanding	3.000s	22.833us	20	20	100.00
V2		TOTAL			681	690	98.70
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	166.830us	20	20	100.00
		spi_host_sec_cm	3.000s	3.849ms	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	166.830us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.09	98.19	95.98	99.74	96.25	95.70	100.00	98.60	91.70

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:

Test spi_host_overflow_underflow has 1 failures.

18.spi_host_overflow_underflow.2035194563
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 43111409642 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf24f3094) == 0x0
  UVM_INFO @ 43111409642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_stress_all has 1 failures.

27.spi_host_stress_all.830270151
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log

  UVM_FATAL @ 13496161343 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4f33b554) == 0x0
  UVM_INFO @ 13496161343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 1 failures.

46.spi_host_smoke.1818495516
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log

  UVM_FATAL @ 99768342779 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7fd9a714) == 0x0
  UVM_INFO @ 99768342779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:

Test spi_host_sw_reset has 3 failures.

26.spi_host_sw_reset.44620652
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10343204652 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3bf5954) == 0x0
  UVM_INFO @ 10343204652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.spi_host_sw_reset.3708741733
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10011006102 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd2894014) == 0x0
  UVM_INFO @ 10011006102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:

Test spi_host_sw_reset has 2 failures.

6.spi_host_sw_reset.4055819167
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 14011817791 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3c0a73d4) == 0x0
  UVM_INFO @ 14011817791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.spi_host_sw_reset.711148617
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10004200290 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x51517e54) == 0x0
  UVM_INFO @ 10004200290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test spi_host_smoke has 1 failures.

8.spi_host_smoke.298607364
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_status_stall has 1 failures.

16.spi_host_status_stall.379196541
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 1 failures:
- Test spi_host_spien has 1 failures.
  - 6.spi_host_spien.3955617363
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
```
  UVM_FATAL @ 27111364298 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6230d54) == 0x1
  UVM_INFO @ 27111364298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```