SPI_HOST Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.767m	51.228ms	49	50	98.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	113.233us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	30.612us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	124.936us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	29.697us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	46.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	30.612us	20	20	100.00
		spi_host_csr_aliasing	4.000s	29.697us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	22.977us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	21.029us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	performance	spi_host_performance	5.000s	30.425us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.567m	3.623ms	48	50	96.00
		spi_host_error_cmd	3.000s	59.951us	50	50	100.00
		spi_host_event	24.333m	128.910ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.150m	7.236ms	49	50	98.00
V2	speed	spi_host_speed	5.150m	7.236ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	5.150m	7.236ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	7.200m	10.001ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	200.248us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.150m	7.236ms	49	50	98.00
V2	full_cycle	spi_host_speed	5.150m	7.236ms	49	50	98.00
V2	duplex	spi_host_smoke	8.767m	51.228ms	49	50	98.00
V2	tx_rx_only	spi_host_smoke	8.767m	51.228ms	49	50	98.00
V2	stress_all	spi_host_stress_all	2.050m	11.311ms	50	50	100.00
V2	spien	spi_host_spien	6.067m	30.830ms	50	50	100.00
V2	stall	spi_host_status_stall	10.483m	34.937ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.233m	1.643ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	45.724us	50	50	100.00
V2	intr_test	spi_host_intr_test	3.000s	20.922us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	68.577us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	68.577us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	113.233us	5	5	100.00
		spi_host_csr_rw	4.000s	30.612us	20	20	100.00
		spi_host_csr_aliasing	4.000s	29.697us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	32.730us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	113.233us	5	5	100.00
		spi_host_csr_rw	4.000s	30.612us	20	20	100.00
		spi_host_csr_aliasing	4.000s	29.697us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	32.730us	20	20	100.00
V2		TOTAL			680	690	98.55
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	308.550us	20	20	100.00
		spi_host_sec_cm	3.000s	115.989us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	308.550us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			819	830	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.05	98.19	95.98	99.74	96.25	95.70	100.00	98.60	90.46

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:

Test spi_host_smoke has 1 failures.

5.spi_host_smoke.3099785838
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log

  UVM_FATAL @ 152164170830 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc9571a94) == 0x0
  UVM_INFO @ 152164170830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_overflow_underflow has 2 failures.

10.spi_host_overflow_underflow.2954517801
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 37816142063 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaf4f2a54) == 0x0
  UVM_INFO @ 37816142063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.spi_host_overflow_underflow.3302580034
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_overflow_underflow/latest/run.log

  UVM_FATAL @ 46553397305 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x500cae14) == 0x0
  UVM_INFO @ 46553397305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 3 failures:

Test spi_host_sw_reset has 3 failures.

5.spi_host_sw_reset.2227304652
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10001328291 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xec556ad4) == 0x0
  UVM_INFO @ 10001328291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.spi_host_sw_reset.2786207665
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10002002872 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x636dbcd4) == 0x0
  UVM_INFO @ 10002002872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test spi_host_status_stall has 2 failures.

5.spi_host_status_stall.2514316344
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.spi_host_status_stall.1716922684
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log

  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 2 failures:

Test spi_host_sw_reset has 2 failures.

27.spi_host_sw_reset.1989814862
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10000743931 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbceb8cd4) == 0x0
  UVM_INFO @ 10000743931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.spi_host_sw_reset.1782020960
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 14887851753 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x88eeff54) == 0x0
  UVM_INFO @ 14887851753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
- Test spi_host_speed has 1 failures.
  - 36.spi_host_speed.562333445
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_speed/latest/run.log
```
  UVM_FATAL @ 107736034055 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x498cee94) == 0x0
  UVM_INFO @ 107736034055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```