SPI_HOST Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.967m	24.106ms	47	50	94.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	48.507us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	34.943us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	1.687ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	34.187us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	21.584us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	34.943us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.187us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	17.520us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	23.455us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	performance	spi_host_performance	4.000s	31.410us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.050m	7.717ms	50	50	100.00
		spi_host_error_cmd	4.000s	53.985us	50	50	100.00
		spi_host_event	20.200m	29.162ms	50	50	100.00
V2	clock_rate	spi_host_speed	5.183m	6.856ms	50	50	100.00
V2	speed	spi_host_speed	5.183m	6.856ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	5.183m	6.856ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.400m	12.009ms	44	50	88.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	163.836us	50	50	100.00
V2	cpol_cpha	spi_host_speed	5.183m	6.856ms	50	50	100.00
V2	full_cycle	spi_host_speed	5.183m	6.856ms	50	50	100.00
V2	duplex	spi_host_smoke	9.967m	24.106ms	47	50	94.00
V2	tx_rx_only	spi_host_smoke	9.967m	24.106ms	47	50	94.00
V2	stress_all	spi_host_stress_all	3.333m	9.456ms	50	50	100.00
V2	spien	spi_host_spien	6.017m	35.964ms	50	50	100.00
V2	stall	spi_host_status_stall	9.583m	27.431ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.233m	1.735ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	21.360us	50	50	100.00
V2	intr_test	spi_host_intr_test	4.000s	76.530us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	148.075us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	148.075us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	48.507us	5	5	100.00
		spi_host_csr_rw	4.000s	34.943us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.187us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	64.866us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	48.507us	5	5	100.00
		spi_host_csr_rw	4.000s	34.943us	20	20	100.00
		spi_host_csr_aliasing	3.000s	34.187us	5	5	100.00
		spi_host_same_csr_outstanding	4.000s	64.866us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	167.614us	20	20	100.00
		spi_host_sec_cm	4.000s	63.949us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	167.614us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			820	830	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	98.19	95.98	99.74	96.34	95.70	100.00	98.60	90.87

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 4 failures:

Test spi_host_sw_reset has 4 failures.

1.spi_host_sw_reset.429552204
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 10818610178 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1dd22954) == 0x0
  UVM_INFO @ 10818610178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.spi_host_sw_reset.1204852665
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 12009436762 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x88158d54) == 0x0
  UVM_INFO @ 12009436762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:

Test spi_host_sw_reset has 2 failures.

37.spi_host_sw_reset.214861173
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 14072748749 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb6b01f14) == 0x0
  UVM_INFO @ 14072748749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.spi_host_sw_reset.1219762794
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log

  UVM_FATAL @ 23576346358 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x77851a54) == 0x0
  UVM_INFO @ 23576346358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_host_smoke has 1 failures.

46.spi_host_smoke.3463778689
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log

  UVM_FATAL @ 72848213600 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa258efd4) == 0x0
  UVM_INFO @ 72848213600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:

Test spi_host_smoke has 2 failures.

4.spi_host_smoke.284277822
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log

  UVM_FATAL @ 147179160689 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xad375e14) == 0x0
  UVM_INFO @ 147179160689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.spi_host_smoke.108149126
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log

  UVM_FATAL @ 159724665290 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd555ca94) == 0x0
  UVM_INFO @ 159724665290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 9.spi_host_status_stall.3017035106
    Line 233, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```