60490355a60490355a| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | performance | spi_host_performance | 22 | 50 | 44.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 0 | 50 | 0.00 |
| spi_host_error_cmd | 3 | 50 | 6.00 | ||
| spi_host_event | 0 | 50 | 0.00 | ||
| V2 | clock_rate | spi_host_speed | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 49 | 50 | 98.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 50 | 50 | 100.00 |
| V2 | full_cycle | full_cycle | 0 | 0 | -- |
| V2 | duplex | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 50 | 50 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 3 | 50 | 6.00 |
| V2 | alert_test | spi_host_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5 | 5 | 100.00 |
| spi_host_csr_rw | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 317 | 540 | 58.70 | |
| V2S | tl_intg_err | spi_host_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | winbond | winbond | 0 | 0 | -- |
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- |
| V3 | TOTAL | 0 | 0 | -- | |
| Unmapped tests | spi_host_mem_walk | 5 | 5 | 100.00 | |
| spi_host_mem_partial_access | 5 | 5 | 100.00 | ||
| TOTAL | 452 | 675 | 66.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 2 | 100.00 |
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 12 | 6 | 46.15 |
| V2S | 2 | 1 | 1 | 50.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.78 | 95.16 | 89.47 | 97.03 | 82.09 | 97.64 | 65.22 | 96.00 | 91.21 |
UVM_WARNING [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory. has 73 failures:
0.spi_host_overflow_underflow.735111397
Line 78, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_overflow_underflow/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.spi_host_overflow_underflow.666670713
Line 78, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_overflow_underflow/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
6.spi_host_stress_all.1059333359
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_stress_all/out/run.log
UVM_WARNING @ 4157358254 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 4157358254 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
9.spi_host_stress_all.3133715984
Line 80, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_stress_all/out/run.log
UVM_WARNING @ 4237635 ps: [BDTYP] Cannot create an object of type 'spi_host_overflow_underflow_vseq' because it is not registered with the factory.
UVM_INFO @ 4237635 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 21 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.txwm has 59 failures:
0.spi_host_event.813021286
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_event/out/run.log
UVM_ERROR @ 3964390 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 3964390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_event.3845874370
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_event/out/run.log
UVM_ERROR @ 2797925 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 2797925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
2.spi_host_stress_all.1336729878
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/out/run.log
UVM_ERROR @ 2292068 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 2292068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_stress_all.259319712
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/out/run.log
UVM_ERROR @ 14838674 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.txwm
UVM_INFO @ 14838674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state has 31 failures:
0.spi_host_error_cmd.4046189767
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_error_cmd/out/run.log
UVM_ERROR @ 11245879 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 11245879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_error_cmd.4012081778
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_error_cmd/out/run.log
UVM_ERROR @ 18704937 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 18704937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
5.spi_host_stress_all.2874131112
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/out/run.log
UVM_ERROR @ 11773134 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 11773134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_stress_all.2656227215
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_stress_all/out/run.log
UVM_ERROR @ 3923999 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.intr_state
UVM_INFO @ 3923999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 19 failures:
4.spi_host_stress_all.3946713523
Line 116, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/out/run.log
UVM_FATAL @ 10532071656 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xb9c55794) == 0x0
UVM_INFO @ 10532071656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_stress_all.731278628
Line 116, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/out/run.log
UVM_FATAL @ 13017468701 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x52facb14) == 0x0
UVM_INFO @ 13017468701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
14.spi_host_performance.2715157278
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_performance/out/run.log
UVM_FATAL @ 10188027843 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x398f8814) == 0x0
UVM_INFO @ 10188027843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_performance.185641949
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_performance/out/run.log
UVM_FATAL @ 10072178564 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xa1a6f6d4) == 0x0
UVM_INFO @ 10072178564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
47.spi_host_sw_reset.4206148537
Line 134, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_sw_reset/out/run.log
UVM_FATAL @ 10133438621 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x40d40fd4) == 0x0
UVM_INFO @ 10133438621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 11 failures:
0.spi_host_performance.2657809150
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_performance/out/run.log
UVM_FATAL @ 10165474246 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6e82d554) == 0x1
UVM_INFO @ 10165474246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_performance.3203954597
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_performance/out/run.log
UVM_FATAL @ 10091001875 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf3026294) == 0x1
UVM_INFO @ 10091001875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
27.spi_host_stress_all.439201867
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_stress_all/out/run.log
UVM_FATAL @ 10177882772 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4de33d54) == 0x1
UVM_INFO @ 10177882772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
1.spi_host_error_cmd.4237283348
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_error_cmd/out/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_error_cmd.3939484778
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_error_cmd/out/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*) == * has 6 failures:
5.spi_host_performance.404450149
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_performance/out/run.log
UVM_FATAL @ 10055585818 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xe4f5b2d4) == 0x0
UVM_INFO @ 10055585818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_performance.350199294
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_performance/out/run.log
UVM_FATAL @ 10048592615 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x1a958d94) == 0x0
UVM_INFO @ 10048592615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
16.spi_host_stress_all.1149659649
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_stress_all/out/run.log
UVM_FATAL @ 10087868136 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x634e7554) == 0x0
UVM_INFO @ 10087868136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:378) [spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 6 failures:
12.spi_host_error_cmd.3912518764
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_error_cmd/out/run.log
UVM_ERROR @ 1914143 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1914143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_error_cmd.2643005239
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_error_cmd/out/run.log
UVM_ERROR @ 13708074 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_error_cmd_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 13708074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.error_status.cmdbusy has 4 failures:
8.spi_host_error_cmd.2405575669
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_error_cmd/out/run.log
UVM_ERROR @ 14945799 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.error_status.cmdbusy
UVM_INFO @ 14945799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_error_cmd.3500204542
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_error_cmd/out/run.log
UVM_ERROR @ 12350665 ps: (csr_utils_pkg.sv:432) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_host_reg_block.error_status.cmdbusy
UVM_INFO @ 12350665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:378) [spi_host_event_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
1.spi_host_stress_all.2707939007
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/out/run.log
UVM_ERROR @ 2454704 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_event_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2454704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_stress_all.1649278613
Line 188, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/out/run.log
UVM_ERROR @ 5080742921 ps: (cip_base_vseq.sv:378) [uvm_test_top.env.virtual_sequencer.spi_host_event_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5080742921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
11.spi_host_performance.3545702208
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_performance/out/run.log
UVM_FATAL @ 10178661994 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcaa2b114) == 0x0
UVM_INFO @ 10178661994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_performance.453222490
Line 98, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_performance/out/run.log
UVM_FATAL @ 10042601192 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2b192294) == 0x0
UVM_INFO @ 10042601192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---