SPI_HOST Simulation Results

Friday May 20 2022 08:02:50 UTC

GitHub Revision: 60490355a
Foundry Revision: 60490355a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1970734642

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke spi_host_smoke 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 5 5 100.00
V1 csr_rw spi_host_csr_rw 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
V1 TOTAL 105 105 100.00
V2 performance spi_host_performance 22 50 44.00
V2 error_event_intr spi_host_overflow_underflow 0 50 0.00
spi_host_error_cmd 3 50 6.00
spi_host_event 0 50 0.00
V2 clock_rate spi_host_speed 50 50 100.00
V2 speed spi_host_speed 50 50 100.00
V2 chip_select_timing spi_host_speed 50 50 100.00
V2 sw_reset spi_host_sw_reset 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 50 50 100.00
V2 cpol_cpha spi_host_speed 50 50 100.00
V2 full_cycle full_cycle 0 0 --
V2 duplex spi_host_smoke 50 50 100.00
V2 tx_rx_only spi_host_smoke 50 50 100.00
V2 stress_all spi_host_stress_all 3 50 6.00
V2 alert_test spi_host_alert_test 50 50 100.00
V2 intr_test spi_host_intr_test 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 5 5 100.00
spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
spi_host_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 5 5 100.00
spi_host_csr_rw 20 20 100.00
spi_host_csr_aliasing 5 5 100.00
spi_host_same_csr_outstanding 20 20 100.00
V2 TOTAL 317 540 58.70
V2S tl_intg_err spi_host_tl_intg_err 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S TOTAL 20 20 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_mem_walk 5 5 100.00
spi_host_mem_partial_access 5 5 100.00
TOTAL 452 675 66.96

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 2 100.00
V1 6 6 6 100.00
V2 13 12 6 46.15
V2S 2 1 1 50.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.78 95.16 89.47 97.03 82.09 97.64 65.22 96.00 91.21

Failure Buckets

Past Results