Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	306061622	1			T1	8390		T2	401808		T3	11860
instr_valid_dis	278303000	1			T1	8390		T2	132120		T3	11860
instr_en	17271694	1			T2	174754		T11	362064		T12	246390

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8542718	1			T2	112198		T11	70898		T12	11332
sram_ifetch_valid_disable	271162515	1			T1	8390		T2	131182		T3	11860
sram_ifetch_enable	26356389	1			T2	158428		T11	64882		T12	137772

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	306061622	1			T1	8390		T2	401808		T3	11860
hw_debug_en_valid_off	271471012	1			T1	8390		T2	194608		T3	11860
hw_debug_en_on	24593232	1			T2	95598		T11	186812		T12	85320

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	271162515	1			T1	8390		T2	131182		T3	11860
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	260758634	1			T1	8390		T2	66620		T3	11860
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7250346	1			T2	27956		T11	226284		T12	97286
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3668818	1			T2	65978		T11	13522		T49	2882
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1949978	1			T6	19268		T125	2764		T34	71456
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1281722	1			T2	23012		T11	13522		T49	2882
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2956796	1			T12	11332		T49	48236		T22	94012
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1011942	1			T23	8062		T6	47324		T124	16570
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1449654	1			T12	11332		T49	48236		T22	94012
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7930090	1			T2	50018		T11	152950		T12	41544
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3513256	1			T2	9992		T23	108016		T5	25470
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3314434	1			T2	20026		T11	152950		T12	41544

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	6722318	1			T2	90066		T11	64882		T12	137772
lc_exec_en	13706346	1			T2	45580		T11	33862		T12	32444
valid_exec_dis	273230891	1			T1	8390		T2	103804		T3	11860
invalid_exec_dis	34899107	1			T2	270626		T11	135780		T12	149104